Patent application number | Description | Published |
20080308921 | MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE - A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other. | 12-18-2008 |
20080318361 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip. | 12-25-2008 |
20090001605 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate having connection pads formed on one surface thereof, a semiconductor chip having bonding pads formed on one surface thereof to correspond to the connection pads; bumps for electrically connecting the connection pads and the bonding pads with each other, a coating layer located on exposed surface portions of the bonding pads and the connection pads to prevent voids from being formed in spaces between the substrate and the semiconductor chip, and an underfill member filled in the spaces over the coating layer. | 01-01-2009 |
20090103374 | MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME - A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set. | 04-23-2009 |
20090121326 | SEMICONDUCTOR PACKAGE MODULE - A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module. | 05-14-2009 |
20090121336 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads. | 05-14-2009 |
20090166836 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 07-02-2009 |
20090230565 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip. | 09-17-2009 |
20090261458 | THROUGH-ELECTRODE, CIRCUIT BOARD HAVING A THROUGH-ELECTRODE, SEMICONDUCTOR PACKAGE HAVING A THROUGH-ELECTRODE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR CHIP OR PACKAGE HAVING A THROUGH-ELECTRODE - A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit. | 10-22-2009 |
20090317944 | MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE - A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other. | 12-24-2009 |
20100059838 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. | 03-11-2010 |
20100066657 | Liquid crystal display - Disclosed herein is a liquid crystal display capable of reducing a side effect during local LED dimming to reduce power consumption and improve display quality. The liquid crystal display includes a liquid crystal panel having a plurality of liquid crystal cells formed respectively in a plurality of pixel areas defined by intersections of a plurality of gate lines and a plurality of data lines, a data driver for supplying data voltages to the data lines, a gate driver for supplying scan signals to the gate lines, a timing controller for controlling the data driver and gate driver and outputting a plurality of dimming signals based on an average picture level (APL) detected based on video data supplied to the liquid crystal panel, and a light emitting diode (LED) backlight unit for partitioning the liquid crystal panel into a plurality of areas and supplying appropriate pulse width modulation (PWM) control signals based on the dimming signals to a plurality of LED arrays installed to correspond respectively to the partitioned areas, to supply light to the liquid crystal panel. | 03-18-2010 |
20100117208 | SEMICONDUCTOR PACKAGE FOR IMPROVING CHARACTERISTICS FOR TRANSMITTING SIGNALS AND POWER - A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants. | 05-13-2010 |
20100258936 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package is presented which includes multiple semiconductor chips and through-electrodes. Each semiconductor chip has bonding pads formed on a first surface of the semiconductor chip and has a projection which projects from a portion of a second surface of the semiconductor chip. The first and second surfaces of the semiconductor chip face away from each other the first surface. The through-electrodes pass through the first surface and through the projection on the second surface. | 10-14-2010 |
20110031600 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate. | 02-10-2011 |
20110121433 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip and a stacked semiconductor package are presented. The semiconductor chip includes a semiconductor substrate, circuit patterns, first input/output pads and second input/output pads. The semiconductor substrate is divided into cell and peripheral regions and has first and second surfaces which oppose each other. The circuit patterns are formed on the first surface of the semiconductor substrate and are connected with the cell region and the peripheral region. The first input/output pads are formed in the cell region and are connected to the circuit patterns. The second input/output pads are formed in the peripheral region and connected with the circuit patterns. | 05-26-2011 |
20110156233 | STACK PACKAGE - A stack package includes a first semiconductor chip possessing a first size and one or more second semiconductor chips possessing a second size greater than the first size. The first semiconductor chip has a first surface on which bonding pads are disposed, a second surface which faces away from the first surface, and first through-electrodes which pass through the first surface and the second surface. The one or more second semiconductor chips are stacked on the second surface of the first semiconductor chip and have second through-electrodes which are electrically connected to the first through-electrodes. A molding part abuts one or more side surfaces of the first semiconductor chip such that a total size including the first size and a size of the molding part is equal to or greater than the second size. | 06-30-2011 |
20110233795 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 09-29-2011 |
20110254145 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads. | 10-20-2011 |
20110287584 | SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts. | 11-24-2011 |
20120009736 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip. | 01-12-2012 |
20120299169 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20120299199 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20130102106 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. | 04-25-2013 |
20140264833 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes through-chip vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate; and a passivation layer formed on the backside of the semiconductor substrate and planarized corresponding to the surface of the protrusions of the through-chip vias, wherein the passivation layer includes a first insulation layer formed on the side of the protrusions of the through-chip vias and the backside of the semiconductor substrate, and a second insulation layer formed over the first insulation layer. | 09-18-2014 |
20140264848 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes through-substrate vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate, and a passivation layer formed on a sidewall of the protrusion and the backside of the semiconductor substrate, wherein a bottom surface of the protrusion and a bottom surface of the passivation layer are substantially coplanar. | 09-18-2014 |