Patent application number | Description | Published |
20090072382 | MICROELECTRONIC PACKAGE AND METHOD OF FORMING SAME - A microelectronic package includes a carrier ( | 03-19-2009 |
20090294942 | PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE - In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed. | 12-03-2009 |
20100207265 | Method of stiffening coreless package substrate - Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material. | 08-19-2010 |
20100258927 | Package-on-package interconnect stiffener - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 10-14-2010 |
20100301492 | METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE - Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material. | 12-02-2010 |
20110101516 | Microelectronic package and method of manufacturing same - A microelectronic package includes a first substrate ( | 05-05-2011 |
20110108947 | Microelectronic device and method of manufacturing same - A microelectronic device comprises a first substrate ( | 05-12-2011 |
20110228464 | SYSTEM-IN-PACKAGE USING EMBEDDED-DIE CORELESS SUBSTRATES, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface. | 09-22-2011 |
20110241215 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 10-06-2011 |
20110281375 | MAGNETIC MICROELECTRONIC DEVICE ATTACHMENT - The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged. | 11-17-2011 |
20110317383 | MOLD COMPOUNDS IN IMPROVED EMBEDDED-DIE CORELESS SUBSTRATES, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus include an at least one stiffener layer that is integral to the coreless substrate and the stiffener layer is made of overmold material, underfill material, or prepreg material. | 12-29-2011 |
20110318850 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a first substrate ( | 12-29-2011 |
20120074581 | DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate. | 03-29-2012 |
20120112336 | ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE - An encapsulated die ( | 05-10-2012 |
20120326271 | SECONDARY DEVICE INTEGRATION INTO CORELESS MICROELECTRONIC DEVICE PACKAGES - The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package. | 12-27-2012 |
20130270715 | PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES - A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. | 10-17-2013 |
20130277865 | MULTI DIE PACKAGE STRUCTURES - Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies. | 10-24-2013 |
20130292838 | PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 11-07-2013 |
20130328207 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 12-12-2013 |
20140084467 | FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. | 03-27-2014 |
20140085846 | MICROELECTRONIC STRUCTURES HAVING LAMINATED OR EMBEDDED GLASS ROUTING STRUCTURES FOR HIGH DENSITY PACKAGING - Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure. | 03-27-2014 |
20140091440 | SYSTEM IN PACKAGE WITH EMBEDDED RF DIE IN CORELESS SUBSTRATE - Electronic assemblies and their manufacture are described. One assembly includes a coreless substrate comprising a plurality of dielectric layers and electrically conductive pathways, the coreless substrate including a first side and a second side opposite the first side. The assembly includes a first die embedded in the coreless substrate, the first die comprising an RF die, the first die positioned in a dielectric layer that extends to the first side of the coreless substrate. The assembly includes a second die positioned on first side, the second die positioned on the first die. In another aspect, a molding material may be positioned on the die side, wherein the first die and the second die are covered by the molding material. In another aspect, an electrical shielding layer may be positioned over the first side. Other embodiments are described and claimed. | 04-03-2014 |
20140091445 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 04-03-2014 |
20140091474 | LOCALIZED HIGH DENSITY SUBSTRATE ROUTING - Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough. | 04-03-2014 |
20140138713 | PASSIVATION LAYER FOR FLEXIBLE DISPLAY - Embodiments of the present disclosure are directed towards passivation techniques and configurations for a flexible display. In one embodiment, a flexible display includes a flexible substrate, an array of display elements configured to emit or modulate light disposed on the flexible substrate, and a passivation layer including molecules of silicon (Si) bonded with oxygen (O) or nitrogen (N), the passivation layer being disposed on the array of display elements to protect the array of display elements from environmental hazards. | 05-22-2014 |
20140138845 | LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS - Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die. | 05-22-2014 |
20140165269 | FLEXIBLE COMPUTING FABRIC - A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa. | 06-19-2014 |
20140168355 | WEARABLE IMAGING SENSOR FOR COMMUNICATIONS - A wearable image sensor is described. In one example, an apparatus includes a camera to capture images with a wide field of view, a data interface to send camera images to an external device, and a power supply to power the camera and the data interface. The camera, data interface, and power supply are attached to a garment that is wearable. | 06-19-2014 |
20140205851 | MAGNETIC CONTACTS FOR ELECTRONICS APPLICATIONS - An interconnect structure for electrically joining two surfaces includes magnetic attachment structures and an anisotropic conductive adhesive (ACA). Magnetic attachment structures on a first surface are magnetically attracted to magnetic attachment structures on a second surface. Opposing magnetic attachment structures are joined via an ACA, which conducts electricity when compressed, and is electrically insulating when not compressed. The magnetic attraction between opposing magnetic attachment structures generates a sufficient force to maintain compression of the intervening ACA in order to sustain a desired level of electrical conductivity between the first surface and second surface. A method for joining two surfaces using the interconnect structure is disclosed. Additionally, a magnetic anisotropic conductive adhesive having magnetic conductive particles dispersed therein is disclosed. | 07-24-2014 |
20140295621 | DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate. | 10-02-2014 |
20140327149 | DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate. | 11-06-2014 |
20150050781 | SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION - Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs. | 02-19-2015 |