Patent application number | Description | Published |
20080244242 | Using a Register File as Either a Rename Buffer or an Architected Register File - A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor is operating. Responsive to determining the thread mode, the instruction dispatch unit determines an ability to use the set of architected register files as the set of temporary rename buffers. Responsive to the ability to use the set of architected register files as the set of temporary rename buffers, the instruction dispatch unit analyzes the instruction to determine an address of an architected register file in the set of architected register files where the instruction data is to be stored. The architected register file operating as a temporary rename buffer stores the instruction data as finished data. | 10-02-2008 |
20130049824 | 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING - There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor. | 02-28-2013 |
20130221484 | THROUGH SILICON VIA NOISE SUPPRESSION USING BURIED INTERFACE CONTACTS - Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise. | 08-29-2013 |
20130234767 | 3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT - There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata. | 09-12-2013 |
20140264593 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 09-18-2014 |
20140264605 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 09-18-2014 |