Patent application number | Description | Published |
20100133599 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 06-03-2010 |
20100155810 | MULTI-LAYER NONVOLATILE MEMORY DEVICES HAVING VERTICAL CHARGE STORAGE REGIONS - Some embodiments of the present invention provide nonvolatile memory devices including a plurality of intergate insulating patterns and a plurality of cell gate patterns that are alternately and vertically stacked on a substrate, an active pattern disposed on the substrate, the active pattern extending upwardly along sidewalls of the intergate insulating patterns and the cell gate patterns, a plurality of charge storage patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, the plurality of the charge storage patterns being separated from each other, tunnel insulating patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, and the tunnel insulating patterns extending to be directly connected to each other and a plurality of blocking insulating patterns disposed between the plurality of cell gate patterns and the plurality of charge storage patterns, respectively. A sidewall of the cell gate pattern may be recessed laterally so that an undercut region is defined and the charge storage pattern is disposed in the undercut region. | 06-24-2010 |
20100163968 | SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 07-01-2010 |
20100178759 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 07-15-2010 |
20110045657 | METHOD FOR FABRICATING REWRITABLE THREE-DIMENSIONAL MEMORY DEVICE - A method for fabricating a three-dimensional semiconductor memory device including three-dimensionally arranged transistors includes forming a thin film structure comprising a plurality of thin films on a semiconductor substrate, patterning the thin film structure such that a penetration region is formed to expose the semiconductor substrate, forming a polycrystalline semiconductor layer to cover the resultant structure where the penetration region is formed, patterning the semiconductor layer to locally form a semiconductor pattern within the penetration region, and performing a post-treatment process to treat the semiconductor layer or the semiconductor pattern with a post-treatment material containing hydrogen or deuterium. | 02-24-2011 |
20110316064 | Semiconductor Memory Devices And Methods Of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region. | 12-29-2011 |
20120064681 | Semiconductor Memory Device And Method Of Forming The Same - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 03-15-2012 |
20120064682 | Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices - Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm | 03-15-2012 |
20120193700 | Semiconductor Memory Device And Method Of Forming The Same - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 08-02-2012 |
20120248525 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided. | 10-04-2012 |
20130134492 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Example embodiments of inventive concepts relate to semiconductor memory devices and/or methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel penetrating the plurality of gates and a data storage layer between the vertical channel and the plurality of gates. The vertical channel may include a lower channel connected to the substrate and an upper channel on the lower channel. The upper channel may include a vertical pattern penetrating some of the plurality of gates and defining an inner space filled with an insulating layer, and a horizontal pattern horizontally extending along a top surface of the lower channel. The horizontal pattern may be in contact with the top surface of the lower channel. | 05-30-2013 |
20130273728 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 10-17-2013 |
20140015128 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 01-16-2014 |
20140162440 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region. | 06-12-2014 |