Patent application number | Description | Published |
20080205142 | ERASE VOLTAGE GENERATOR CIRCUIT FOR PROVIDING UNIFORM ERASE EXECUTION TIME AND NONVOLATILE MEMORY DEVICE HAVING THE SAME - An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal. | 08-28-2008 |
20080224752 | INTERNAL CLOCK GENERATOR, SYSTEM AND METHOD - An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection. | 09-18-2008 |
20080285355 | FLASH MEMORY DEVICE AND METHOD OF ERASING FLASH MEMORY DEVICE - A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during an erase operation. | 11-20-2008 |
20080310226 | Multi-Bit Flash Memory Devices Having a Single Latch Structure and Related Programming Methods, Systems and Memory Cards - Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed. | 12-18-2008 |
20080316819 | FLASH MEMORY DEVICE CAPABLE OF STORING MULTI-BIT DATA AND SINGLE-BIT DATA - There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included. | 12-25-2008 |
20090019215 | Method and device for performing cache reading - Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. | 01-15-2009 |
20090135658 | Flash memory device and read method thereof - A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic. | 05-28-2009 |
20090154281 | SEMICONDUCTOR DEVICE WITH REDUCED STANDBY FAILURES - A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode. | 06-18-2009 |
20090175087 | METHOD OF VERIFYING PROGRAMMING OPERATION OF FLASH MEMORY DEVICE - A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete. | 07-09-2009 |
20100001710 | REFERENCE VOLTAGE GENERATING CIRCUIT - A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage. | 01-07-2010 |
20100067312 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written. | 03-18-2010 |
20100110796 | METHOD OF PERFORMING ERASE OPERATION IN NON-VOLATILE MEMORY DEVICE - A method of performing an erase operation in a non-volatile memory device includes a multi-erase operation and a post-erase operation. The multi-erase operation includes multi-erasing multiple memory blocks at the same time using a multi-erase voltage. The post-erase operation includes post-erasing one or more failed memory blocks of the multi-erased memory blocks using a post-erase voltage having sequentially increasing voltage values based on incremental step pulses (ISPs). | 05-06-2010 |
20110205797 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 08-25-2011 |
20110219179 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING BUFFER MEMORY - A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory. | 09-08-2011 |
20110299343 | NON-VOLATILE MEMORY DEVICE, PRECHARGE VOLTAGE CONTROLLING METHOD THEREOF, AND SYSTEM INCLUDING THE SAME - A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period in a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at the third level during a precharge period in a verify read or erase operation. | 12-08-2011 |
20120239866 | NON-VOLATILE MEMORY WITH ERROR CORRECTION FOR PAGE COPY OPERATION AND METHOD THEREOF - The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer. | 09-20-2012 |
20130114338 | VOLTAGE SUPPLY CONTROLLER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied. | 05-09-2013 |
20130128662 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING DATA IN NONVOLATILE MEMORY DEVICE - A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs. | 05-23-2013 |
20130238843 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 09-12-2013 |
20140133227 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING - A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block. | 05-15-2014 |