Patent application number | Description | Published |
20130264656 | Memory Device Having Electrically Floating Body Transistor - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. | 10-10-2013 |
20140198551 | Content Addressable Memory Device Having Electrically Floating Body Transistor - A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. | 07-17-2014 |
20140252451 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided. | 09-11-2014 |
20140328128 | NAND String Utilizing Floating Body Memory Cell - NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. | 11-06-2014 |
20150023105 | Memory Cell Comprising First and Second Transistors and Methods of Operating - Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series. | 01-22-2015 |
20150200005 | Memory Device Comprising an Electrically Floating Body Transistor - A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region. | 07-16-2015 |
20150221653 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided. | 08-06-2015 |
20160049190 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. | 02-18-2016 |
20160086954 | Memory Device Having Electrically Floating Body Transistor - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. | 03-24-2016 |