Patent application number | Description | Published |
20090103625 | VIDEO ENCODING APPARATUS AND METHOD USING PIPELINE TECHNIQUE WITH VARIABLE TIME SLOT - A video encoding apparatus and method using a pipeline technique with a variable time slot are provided. More particularly, a video encoding apparatus and method capable of shortening a video encoding time by variably adjusting lengths of time slots when an H.264 video encoding process is performed in a pipeline structure are provided. The video encoding apparatus includes a plurality of functional blocks that perform video encoding steps based on an H.264 standard for macroblocks configuring input digital video signals in a pipeline structure, and a controller that controls lengths of time slots configuring the pipeline structure based on done signals received from the plurality of functional blocks. Lengths of time slots can be adjusted according to operation times of video encoding steps using done signals generated from functional blocks, thereby preventing unnecessary power consumption and delays when using a fixed-length time slot. | 04-23-2009 |
20090154564 | MOTION ESTIMATION APPARATUS AND METHOD FOR MOVING PICTURE CODING - Provided is a motion estimation apparatus for moving picture coding. The apparatus includes a 1-pel buffer for storing 1-pel unit pixels using luminance signals of a reference frame which correspond to macroblocks of a current frame, a 1-pel estimator for calculating 1-pel unit motion vectors and minimum costs in correspondence to the macroblocks of the current frame and the pixels stored in the 1-pel buffer, a ½-pel interpolator for performing ½-pel unit interpolation using the pixels stored in the 1-pel buffer, a ½-pel buffer for storing the ½-pel unit interpolated pixels, a ½-pel estimator for calculating ½-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ½-pel buffer, the values calculated by the 1-pel estimator, and the macroblocks of the current frame, a ¼-pel interpolator for performing ¼-pel unit interpolation using the pixels stored in the ½-pel and 1-pel buffers, a ¼-pel buffer for storing the ¼-pel unit interpolated pixels, and a ¼-pel estimator for calculating ¼-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ¼-pel buffer, the values calculated by the ½-pel estimator, and the macroblocks of the current frame. | 06-18-2009 |
20110064137 | VIDEO ENCODING APPARATUS - There is provided a video encoding apparatus allowing for enhanced video encoding speed according to the H.264 video coding standard. The video encoding apparatus allows the memories included in the video encoding apparatus to be shared by a plurality of elements through the rearrangement and the structural change of the memories considering an efficient hierarchical motion estimation algorithm. Therefore, the video encoding apparatus has the effects of reducing the amount of transmitted and received data between the frame memory and the video encoding apparatus and enhancing video encoding speed. | 03-17-2011 |
20110135008 | VIDEO PROCESSING SYSTEM - A video processing system includes a frame memory, an input video buffer, a macroblock buffer, a first search window buffer, a second search window buffer, a deblocked macroblock buffer, and a frame memory controller. The frame memory stores frame data. The input video buffer stores input data and transfers the input data to the frame memory. The macroblock buffer stores a plurality of macroblocks. The first search window buffer stores a search region of a reference frame for coarse motion estimation. The second search window buffer stores a search region of a reference frame for fine motion estimation. The deblocked macroblock buffer stores the performance results of a deblocking filter. The frame memory controller performs write/read operations on the input video buffer, the macroblock buffer, the first search window buffer, the second search window buffer, the deblocked macroblock buffer and the frame memory. | 06-09-2011 |
20120131356 | APPARATUS FOR CONTROLLING POWER OF MULTI CORE PROCESSOR AND METHOD THEREOF - The present invention relates to an apparatus for controlling power of mufti core processor, which includes a power control device by core unit, controls a plurality of power-related parameters by core unit, and thus decreases a load for power management and enables realization of a low power multi core processor through minute power control. The apparatus includes a processor core adapted to provide code information on an application program for executing to a power regulation controller, and a power regulation controller adapted to receive the code information on the application program from the processor core to determine an operation frequency of the processor core, set an operation voltage, a clock-gating value and a power-gating value according to the determined operation frequency, and provide the set values and voltage to the processor core. | 05-24-2012 |
20130238859 | CACHE WITH SCRATCH PAD MEMORY STRUCTURE AND PROCESSOR INCLUDING THE CACHE - Disclosed are a cache with a scratch pad memory (SPM) structure and a processor including the same. The cache with a scratch pad memory structure includes: a block memory configured to include at least one block area in which instruction codes read from an external memory are stored; a tag memory configured to store an external memory address corresponding to indexes of the instruction codes stored in the block memory; and a tag controller configured to process a request from a fetch unit for the instruction codes, wherein a part of the block areas is set as a SPM area according to cache setting input from a cache setting unit. According to the present invention, it is possible to reduce the time to read instruction codes from the external memory and realize power saving by operating the cache as the scratch pad memory. | 09-12-2013 |
20140082300 | APPARATUS AND METHOD FOR MAINTAINING CACHE COHERENCY, AND MULTIPROCESSOR APPARATUS USING THE METHOD - Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified. | 03-20-2014 |
20140344623 | APPARATUS AND METHOD FOR DETECTING FAULT OF PROCESSOR - An apparatus and method for detecting the fault of a processor are disclosed. The apparatus includes a fetch fault control unit, a decoding fault control unit, and an execution fault control unit. The fetch fault control unit detects the fault of each of fetch units of a plurality of processor cores connected to memory. The decoding fault control unit detects the fault of each of decoding units of the plurality of processor cores connected to the memory. The execution fault control unit detects the fault of each of execution units of the plurality of processor cores connected to the memory, executes the same instruction in the plurality of processor cores, determines a processor core where a fault has occurred, and provides notification of the determined processor to the fetch fault control unit and the decoding fault control unit. | 11-20-2014 |