Patent application number | Description | Published |
20090287321 | CONFIGURATION SYSTEM USING SECURITY OBJECTS IN A PROCESS PLANT - A configuration system uses process plant items that may represent, or be capable of representing, entities in a process plant to assist in configuring, organizing, and changing the control and display activities within the process plant. Access to the items may be controlled by associating access control data with the items. The configuration system may also use objects that represent, or may be capable of representing, one or more steps to be performed by entities in the process plant. Access to these objects may be controlled by associating access control data with the objects. The access control data may indicate whether users or certain users may be able to, for example, view or modify all or some data associated with the process plant items or the objects. The process plant items may comprise, for example, module class objects which may be capable of generically representing process entities of the process plant, module objects which may be capable of specifically representing process entities of the process plant, composite templates, module templates, etc. The objects that represent, or may be capable of representing, one or more steps to be performed by entities in the process plant may comprise, for example, phase classes or unit phases. | 11-19-2009 |
20100020810 | Link Services in a Communication Network - In a communication network, links in a transmission path between source and destination terminals are sequentially switched to an operational state in response to a command or a group of commands for transmitting data prior to completion of assembling the data. Each node in the transmission path independently monitors transmission of data. After transmitting the data, the links are selectively switched to pre-determined power saving states. | 01-28-2010 |
20100115204 | NON-UNIFORM CACHE ARCHITECTURE (NUCA) - In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory. | 05-06-2010 |
20100228373 | VERSION CONTROL FOR OBJECTS IN A PROCESS PLANT CONFIGURATION SYSTEM - A version control system helps to keep track of versions of process plant items that may represent, or be capable of representing, entities in a process plant. The process plant items may comprise, for example, module objects which may be capable of specifically representing process entities of the process plant. These module objects may be created from module class objects which may be capable of generically representing process entities of the process plant. Version data is stored and associated with a module object. The version data may comprise data indicative of a version of a module class object that was used to create the module object. The version data may also comprise data indicative of a version of the module object. Configuration systems, version control systems, viewing systems, debugging systems, run-time monitoring systems, asset management systems, etc., may examine or permit viewing of the version control data associated with an item. | 09-09-2010 |
20100332761 | Reconfigurable Cache - A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power. | 12-30-2010 |
20110072214 | Read and Write Aware Cache - A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy. | 03-24-2011 |
20110119322 | On-Chip Networks for Flexible Three-Dimensional Chip Integration - Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer. | 05-19-2011 |
20110224808 | Security for Objects in a Process Plant Configuration System - A configuration system uses process plant items that may represent, or be capable of representing, entities in a process plant to assist in configuring, organizing, and changing the control and display activities within the process plant. Access to the items may be controlled by associating access control data with the items. The configuration system may also use objects that represent, or may be capable of representing, one or more steps to be performed by entities in the process plant. Access to these objects may be controlled by associating access control data with the objects. The access control data may indicate whether users or certain users may be able to, for example, view or modify all or some data associated with the process plant items or the objects. The process plant items may comprise, for example, module class objects which may be capable of generically representing process entities of the process plant, module objects which may be capable of specifically representing process entities of the process plant, composite templates, module templates, etc. The objects that represent, or may be capable of representing, one or more steps to be performed by entities in the process plant may comprise, for example, phase classes or unit phases. | 09-15-2011 |
20110292594 | Scalable Space-Optimized and Energy-Efficient Computing System - A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame. | 12-01-2011 |
20110296107 | Latency-Tolerant 3D On-Chip Memory Organization - A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access. | 12-01-2011 |
20110296112 | Reducing Energy Consumption of Set Associative Caches by Reducing Checked Ways of the Set Association - Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may be performed: determining if a cache hit occurs in a preferred cache line without accessing other cache lines in the set of cache lines; retrieving data from the preferred cache line without accessing the other cache lines in the set of cache lines, if it is determined that there is a cache hit in the preferred cache line; and accessing each of the other cache lines in the set of cache lines to determine if there is a cache hit in any of these other cache lines only in response to there being a cache miss in the preferred cache line(s). | 12-01-2011 |
20110296149 | Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs - Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction. | 12-01-2011 |
20110296434 | Techniques for Dynamically Sharing a Fabric to Facilitate Off-Chip Communication for Multiple On-Chip Units - A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units. | 12-01-2011 |
20120227051 | Composite Contention Aware Task Scheduling - A mechanism is provided for composite contention aware task scheduling. The mechanism performs task scheduling with shared resources in computer systems. A task is a group of instructions. A compute task is a group of compute instructions. A memory task, also referred to as a communication task, may be a group of load/store operations, for example. The mechanism performs composite contention-aware scheduling that considers the interaction among compute tasks, communication tasks, and application threads that include compute and communication tasks. The mechanism performs a composite of memory task throttling and application thread throttling. | 09-06-2012 |
20120254603 | Run-Ahead Approximated Computations - Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines. | 10-04-2012 |
20120254604 | Run-Ahead Approximated Computations - Mechanisms are provided for performing approximate run-ahead computations. A first group of compute engines is selected to execute full computations on a full set of input data. A second group of compute engines is selected to execute computations on a sampled subset of the input data. A third group of compute engines is selected to compute a difference in computation results between first computation results generated by the first group of compute engines and second computation results generated by the second group of compute engines. The second group of compute engines is reconfigured based on the difference generated by the third group of compute engines. | 10-04-2012 |
20120311265 | Read and Write Aware Cache - A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement polity. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is place in one of the closer banks. The size ration between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy. | 12-06-2012 |
20120317582 | Composite Contention Aware Task Scheduling - A mechanism is provided for composite contention aware task scheduling. The mechanism performs task scheduling with shared resources in computer systems. A task is a group of instructions. A compute task is a group of compute instructions. A memory task, also referred to as a communication task, may be a group of load/store operations, for example. The mechanism performs composite contention-aware scheduling that considers the interaction among compute tasks, communication tasks, and application threads that include compute and communication tasks. The mechanism performs a composite of memory task throttling and application thread throttling. | 12-13-2012 |
20130145210 | FLEXIBLE REPLICATION WITH SKEWED MAPPING IN MULTI-CORE CHIPS - For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core. | 06-06-2013 |
20130145211 | FLEXIBLE REPLICATION WITH SKEWED MAPPING IN MULTI-CORE CHIPS - For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core. | 06-06-2013 |
20140122429 | DATA PROCESSING METHOD AND APPARATUS FOR DISTRIBUTED SYSTEMS - A data processing method for a distributed system, the distributed system comprising a master storage node and multiple slave storage nodes, includes: storing, responsive to a request for writing a data file, multiple replications of the data file on the multiple slave storage nodes, each of the replications being segmented into data blocks of a same size, wherein the sizes of the segmented data blocks of at least two replications are different; and storing distribution information of the multiple replications. | 05-01-2014 |
20140201573 | DEFECT ANALYSIS SYSTEM FOR ERROR IMPACT REDUCTION - An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to analyze a first set of data associated with a plurality of data sources. Analyzing the first set of data associated with the plurality of data sources determines a plurality of relationships among the first set of data. The processor is configured to store indications of the plurality of relationships among the first set of data. An indication of a relationship indicates a possible software defect. The processor is configured to generate rules based, at least in part, on the first set of data associated with a plurality of data sources. A rule indicates a possible software defect. | 07-17-2014 |
20140337357 | DOCUMENT TAGGING AND RETRIEVAL USING PER-SUBJECT DICTIONARIES INCLUDING SUBJECT-DETERMINING-POWER SCORES FOR ENTRIES - Techniques for managing big data include tagging of documents and subsequent retrieval using per-subject dictionaries having entries with subject-determining-power scores. The subject-determining-power scores provide an indication of the descriptive power of the term with respect to the subject of the dictionary containing the term. The same term may have entries in multiple dictionaries with different subject-determining-power scores in each of the dictionaries. A retrieval request for one or more documents containing search terms descriptive of the one or more documents can be processed identifying a set of candidate documents tagged with subjects and optional terms, and then applying subject-determining-power scores from the multiple dictionaries for the search term to determine a subject for the search term. The method then selects the one or more documents from the candidate documents according to the subject. | 11-13-2014 |
20140359635 | PROCESSING DATA BY USING SIMULTANEOUS MULTITHREADING - A computer implemented method and system for data processing. The method including: (a) setting at least one SMT preliminary value for at least one operating node; (b) monitoring performance metrics for the at least one operating node set to the at least one SMT preliminary value; and (c) determining a SMT revised value based on performance metrics. The system including: a memory; a processor communicatively coupled to the memory; and a feature selection module communicatively coupled to the memory and processor, wherein the feature selection module is configured to perform steps of a method including: setting, using a setting device, at least one SMT preliminary value for at least one operating node; monitoring, using a monitoring device, performance metrics for the at least one operating node set to the at least one SMT preliminary value; and determining, using a determining device, a SMT revised value based on performance metrics. | 12-04-2014 |