Patent application number | Description | Published |
20080308913 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove. | 12-18-2008 |
20090026596 | LEAD FRAME, SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - In certain embodiments, a lead frame includes a paddle, a plurality of inner leads, first outer leads, and a second outer lead. The plurality of inner leads can be arranged at a side face of the paddle. The first outer leads can extend from the inner leads along a first direction and can be arranged at a substantially central portion of the side face of the paddle. Furthermore, each of the first outer leads can have a first area. The second outer lead can be arranged at an edge portion of the side face of the paddle and can be supported by the paddle. The second outer lead can have a second area that is larger than the first area. | 01-29-2009 |
20090188704 | MOUNTING SUBSTRATE - A mounting substrate includes a substrate, a bonding pad and an induction heating pad. The bonding pad is formed on the substrate, and adhered to a solder ball to mount a semiconductor chip on the substrate. The induction heating pad is disposed adjacent to the bonding pad, the induction heating pad being induction heated by an applied alternating magnetic field to reflow the solder ball. The induction heating pad having a diameter greater than a skin depth in response to the frequency of the applied alternating magnetic field is selectively induction heated in response to a low frequency band of the alternating magnetic field. Accordingly, during a reflow process for a solder ball, the semiconductor chip may be mounted on the mounting substrate to complete a semiconductor package without damaging the mounting substrate, to thereby improve the reliability of the completed semiconductor package. | 07-30-2009 |
20100096754 | Semiconductor package, semiconductor module, and method for fabricating the semiconductor package - Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line. | 04-22-2010 |
20100117213 | COIL AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An apparatus to package a semiconductor chip includes a coil configured to use induction heating to reflow a solder ball of the semiconductor chip. The coil includes a first body, a second body parallel to the first body, a third body extending from the first body to the second body. The first and second bodies are symmetrical with respect to a vertical plane disposed therebetween. The first and second bodies have inclined surfaces facing each other, and the inclined surfaces are distant from each other downward. | 05-13-2010 |
20100144137 | METHOD OF INTERCONNECTING CHIPS USING CAPILLARY MOTION - A method of interconnecting semiconductor devices by using capillary motion, thereby simplifying fabricating operations, reducing fabricating costs, and simultaneously filling of through-silicon-vias (TSVs) and interconnecting semiconductor devices. The method includes preparing a first semiconductor device in which first TSVs are formed, positioning solder balls respectively on the first TSVs, performing a back-lap operation on the first semiconductor device, positioning a second semiconductor device, in which second TSVs are formed, above the first semiconductor device on which the solder balls are positioned, and performing a reflow operation such that the solder balls fill the first and second TSVs due to capillary motion. | 06-10-2010 |
20100181293 | Reflow apparatus, Reflow method, and package apparatus - Provided is an apparatus for performing a reflow process of a solder ball provided to a semiconductor chip. The reflow apparatus may include a coil, a support member and a moving member. The coil may receive a current from a power supply to heat the solder ball using an induced heating method. The support member may be disposed on the front or the rear of the coil and may support a printed circuit board on which a semiconductor chip is mounted. The moving member may move the printed circuit board so that the printed circuit object passes through an internal space surrounded by the coil. | 07-22-2010 |
20110318876 | SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring. | 12-29-2011 |
20120234497 | DEBONDER TO MANUFACTURE SEMICONDUCTOR AND DEBONDING METHOD THEREOF - A debonder to manufacture a semiconductor that includes: a stage to support a carrier wafer that is attached to a chip stack assembly by a temporary adhesive layer coated on the surface of the carrier wafer; a chuck arranged above the stage to selectively secure the chip stack assembly; a lifting unit to lift the chuck from the stage; a lateral driving unit to move the chuck laterally with respect to the stage; and a controller to control the lifting unit and the lateral driving unit. | 09-20-2012 |
20120313244 | SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring. | 12-13-2012 |
20130258188 | BI-DIRECTIONAL CAMERA MODULE AND FLIP CHIP BONDER INCLUDING THE SAME - Bi-directional camera modules and flip chip bonders including the same are provided. The module includes a circuit board on which an upper sensor and a lower sensor are mounted, an upper lens and a lower lens disposed on the upper sensor and under the lower sensor, respectively, and a housing fixing the upper lens and the lower lens spaced apart from the upper sensor and the lower sensor, respectively. The housing surrounds the circuit board. The housing has a plurality of inlets and an outlet through which air flows, and the housing has an air passage connected from the inlets to the outlet via a space between lower lens and the lower sensor. | 10-03-2013 |
20130299969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening. | 11-14-2013 |
Patent application number | Description | Published |
20130193588 | SEMICONDUCTOR PACKAGE - A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer. | 08-01-2013 |
20130344627 | METHOD OF FABRICATING WAFER LEVEL PACKAGE - A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed. | 12-26-2013 |
20140084456 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES, AND SYSTEMS INCLUDING SEMICONDUCTOR PACKAGES - A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers. | 03-27-2014 |
20140239478 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink. | 08-28-2014 |
20140299980 | SEMICONDUCTOR PACKAGES INCLUDING A HEAT SPREADER AND METHODS OF FORMING THE SAME - Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer. | 10-09-2014 |