Patent application number | Description | Published |
20100290304 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal. | 11-18-2010 |
20100332925 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver. | 12-30-2010 |
20110004794 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal. | 01-06-2011 |
20110235443 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal. | 09-29-2011 |
20120155203 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND SYSTEM OF TESTING THE SAME - A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal. | 06-21-2012 |
20120188839 | BANK SELECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal. | 07-26-2012 |
20120204070 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data. | 08-09-2012 |
20120269017 | DELAY CIRCUIT AND LATENCY CONTROL CIRCUIT OF MEMORY, AND SIGNAL DELAY METHOD THEREOF - A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal. | 10-25-2012 |
20130003482 | SELF-REFRESH CONTROL CIRCUIT AND MEMORY INCLUDING THE SAME - An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device. | 01-03-2013 |
20140068321 | MEMORY DEVICE AND INTEGRATED CIRCUIT - A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages. | 03-06-2014 |
20140313840 | INTEGRATED CIRCUIT AND MEMORY DEVICE - An integrated circuit includes a programmable storage unit suitable for operating with a plurality of powers and outputting stored data in response to a boot-up signal, a register unit suitable for storing the data outputted from the programmable storage unit, a internal circuit suitable for operating by using the data stored in the register unit, a voltage detection unit suitable for activating a power stabilization signal when levels of the plurality of powers are stabilized, and a boot-up control unit suitable for counting a number of activations of a periodic wave from a time of an activation of the power stabilization signal and activating the boot-up signal when the counted number reaches a predetermined number. | 10-23-2014 |
20140369106 | SEMICONDUCTOR DEVICE WITH FUSE ARRAY AND OPERATING METHOD THEREOF - A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal. | 12-18-2014 |