Patent application number | Description | Published |
20100314709 | LATCH-UP PREVENTION STRUCTURE AND METHOD FOR ULTRA-SMALL HIGH VOLTAGE TOLERANT CELL - A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level. | 12-16-2010 |
20130083436 | ELECTROSTATIC DISCHARGE PROTECTION - A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip. | 04-04-2013 |
20130168732 | Vertical BJT and SCR for ESD - An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR). | 07-04-2013 |
20130193526 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 08-01-2013 |
20130234250 | FinFET-Based ESD Devices and Methods for Forming the Same - A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material. | 09-12-2013 |
20140027815 | Fast Turn On Silicon Controlled Rectifiers for ESD Protection - Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal. | 01-30-2014 |
20140126089 | ELECTROSTATIC DISCHARGE PROTECTION FOR THREE DIMENSIONAL INTEGRATED CIRCUIT - The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line. | 05-08-2014 |
20140139958 | ESD PROTECTION CIRCUITS AND METHODS - An electrostatic discharge protection circuit includes a first LC resonator circuit coupled to an input node and disposed in parallel with an internal circuit that is also coupled to the input node, and a second LC resonator circuit coupled in series with the first LC resonator circuit at a first node. The first LC resonator circuit is configured to resonate at a different frequency than a frequency the second LC resonator circuit is configured to resonate. | 05-22-2014 |
20140151809 | APPARATUS FOR ESD PROTECTION - A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region. | 06-05-2014 |
20140159206 | Methods and Apparatus for ESD Structures - Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type. | 06-12-2014 |
20140175551 | Apparatus for ESD Protection - A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region. | 06-26-2014 |
20140193959 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 07-10-2014 |
20140252476 | Rotated STI Diode on FinFET Technology - A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode. | 09-11-2014 |
20140264616 | Epitaxial Growth Between Gates - An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate devices. The device further includes at least one dummy gate between two epitaxially grown active regions. Each active region is substantially uniform in length. | 09-18-2014 |
20140268439 | ELECTROSTATIC DISCHARGE (ESD) CONTROL CIRCUIT - One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current. | 09-18-2014 |
20140268448 | METHOD AND APPARATUS OF ESD PROTECTION IN STACKED DIE SEMICONDUCTOR DEVICE - An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies. | 09-18-2014 |
20140299943 | FinFET-Based ESD Devices and Methods for Forming the Same - A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material. | 10-09-2014 |
20140307355 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD FOR RADIO FREQUENCY CIRCUIT - An ESD protection circuit for an RF circuit includes first and second power supply voltage terminals for first and second power supply voltages and a power clamp coupled between the terminals. An RF input pad is configured to receive an input signal having an RF operating frequency. A resonance circuit is coupled to the RF input pad. A first ESD current path from the RF input pad to the first power supply voltage terminal includes the resonance circuit and a first ESD block configured to direct an ESD pulse of a first polarity toward the first terminal. A second ESD current path from the RF input pad to the second power supply voltage terminal includes the resonance circuit and a second ESD block configured to direct an ESD pulse of a second polarity toward the second terminal. | 10-16-2014 |
20150084134 | FinFET-Based ESD Devices and Methods for Forming the Same - A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region. | 03-26-2015 |
20150084154 | Methods and Apparatus for ESD Structures - Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type. | 03-26-2015 |