Patent application number | Description | Published |
20100015776 | Shallow Trench Isolation Corner Rounding - A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration. | 01-21-2010 |
20110012210 | Scaling EOT by Eliminating Interfacial Layers from High-K/Metal Gates of MOS Devices - An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer. | 01-20-2011 |
20110193178 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-11-2011 |
20110241084 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 10-06-2011 |
20130043507 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 02-21-2013 |
20130196478 | Bottom-Notched SiGe FinFET Formation Using Condensation - An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width. | 08-01-2013 |
20140187011 | Methods for Forming FinFETs with Self-Aligned Source/Drain - A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess. | 07-03-2014 |
20140187013 | Methods for Forming FinFETs Having Multiple Threshold Voltages - A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively. | 07-03-2014 |
20140252475 | FinFETs and Methods for Forming the Same - A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned. | 09-11-2014 |
20140264494 | Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier - A method includes depositing a first metal layer on a native SiO | 09-18-2014 |