Jeddeloh, US
Alan Jeddeloh, Portland, OR US
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20130205016 | REMOTE MONITORING AND CONTROLLING OF NETWORK UTILIZATION - A non-transitory computer-readable storage medium storing instructions which, when executed by processors, cause the processors to perform: at a management computer, receiving, from a gateway located in a managed network, device information about devices in the managed network; for a particular device: determining a match between the device capabilities of the particular device and features of a particular network software application configured to control the particular device, and determining a particular protocol endpoint configured to communicate control instructions from the particular network software application to the particular device; receiving, from the gateway, aggregated data that reflects network utilization by the devices located in the managed network; for the particular device: based at least in part on the aggregated data, using the particular network software application, determining control instructions for the particular device; causing the particular protocol endpoint to transmit the control instructions for the particular device to the device. | 08-08-2013 |
Jeff Jeddeloh, Verona, WI US
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20100167952 | SUPPRESSION OF SECONDARY CAPTURE IN MICROARRAY ASSAYS - The present invention provides for compositions, methods and systems for targeted sequence enrichment. In particular, the present invention provides for enriching for targeted nucleic acid sequences during hybridizations in microarray assays by suppressing secondary capture of non-target nucleic acid sequences. | 07-01-2010 |
20100331204 | METHODS AND SYSTEMS FOR ENRICHMENT OF TARGET GENOMIC SEQUENCES - The present invention provides methods and systems for targeted nucleic acid sequence enrichment in a sample. In particular, the present invention provides for enriching for targeted nucleic acid sequences during hybridizations in hybridization assays by first depleting non-target nucleic acid sequences. | 12-30-2010 |
Jeffrey Jeddeloh, Verona, WI US
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20090203540 | Methods and Systems for Quality Control Metrics in Hybridization Assays - The present invention provides methods and systems for performing quality control metrics in hybridization assays. In particular, the present invention provides for quality control metrics for nucleic acid enrichment on hybridization assay formats, such as microarray assays. | 08-13-2009 |
20090221438 | METHODS AND SYSTEMS FOR UNIFORM ENRICHMENT OF GENOMIC REGIONS - The present invention provides methods and compositions for the enrichment of target nucleic acids in a microarray system. In particular, the present invention provides methods and compositions for uniform enrichment of target nucleic acid molecules in a microarray format. The present invention also provides for intentionally non-uniform enrichment among target nucleic acid molecules. | 09-03-2009 |
20100222232 | ENRICHMENT AND SEQUENCE ANALYSIS OF GENOMIC REGIONS - The present invention provides novel methods for reducing the complexity of preferably a genomic sample for further analysis such as direct DNA sequencing, resequencing or SNP calling. The methods use pre-selected immobilized oligonucleotide probes to capture target nucleic acid molecules from a sample containing denatured, fragmented (genomic) nucleic acids for reducing the genetic complexity of the original population of nucleic acid molecules. | 09-02-2010 |
20110003701 | System and method for improved processing of nucleic acids for production of sequencable libraries - An embodiment of an adaptor element for efficient target processing is described that comprises a semi-complementary double stranded nucleic acid adaptor comprising a non-complementary region and a complementary region, where the non-complementary region comprises a first amplification primer site and a second amplification primer site and the complementary region comprises a sequencing primer site and one or more inosine species. | 01-06-2011 |
20120071357 | METHODS AND SYSTEMS FOR UNIFORM ENRICHMENT OF GENOMIC REGIONS - The present invention provides methods and compositions for the enrichment of target nucleic acids in a microarray system. In particular, the present invention provides methods and compositions for uniform enrichment of target nucleic acid molecules in a microarray format. The present invention also provides for intentionally non-uniform enrichment among target nucleic acid molecules. | 03-22-2012 |
Jeffrey Jeddeloh, Madison, WI US
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20150141256 | COMPOSITIONS AND METHODS FOR BISULFITE CONVERTED SEQUENCE CAPTURE - This invention relates generally to composition and methods for characterizing a methylome which comprises all or substantially all methylation states of a genome. In particular, a plurality of oligonucleotides, each representing nearly every possible methylation state of the cytosine position of each CG dinucleotide pair within a target nucleic acid of interest, and methods of using the plurality are provided herein. | 05-21-2015 |
Joe Jeddeloh, Shoreview, MN US
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20090319714 | SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit. | 12-24-2009 |
20100250826 | MEMORY SYSTEMS WITH A PLURALITY OF STRUCTURES AND METHODS FOR OPERATING THE SAME - Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability. | 09-30-2010 |
20110191517 | SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit. | 08-04-2011 |
Joseph Jeddeloh, Shoreview, MN US
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20090187714 | MEMORY HUB AND ACCESS METHOD HAVING INTERNAL PREFETCH BUFFERS - A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices. | 07-23-2009 |
20140029325 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 01-30-2014 |
Joseph Jeddeloh, Minneapolis, MN US
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20110032261 | METHOD OF IMPLEMENTING AN ACCELERATED GRAPHICS PORT FOR A MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM - An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions. | 02-10-2011 |