Patent application number | Description | Published |
20130027105 | NON-OVERLAP CIRCUIT - A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal. | 01-31-2013 |
20130043541 | LOW POWER/HIGH SPEED TSV INTERFACE DESIGN - A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage. | 02-21-2013 |
20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
20130162331 | DIODE STRING VOLTAGE ADAPTER - A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated. | 06-27-2013 |
20130307516 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage. | 11-21-2013 |
20130328162 | HOMO-JUNCTION DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING - Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells. | 12-12-2013 |
20130328614 | DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS - A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction. | 12-12-2013 |
20140042585 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device. | 02-13-2014 |
20140077230 | DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS - A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction. | 03-20-2014 |
20140077331 | DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING AND METHOD OF FORMING THE SAME - A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate. | 03-20-2014 |
20140103494 | Nearly Buffer Zone Free Layout Methodology - The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation. | 04-17-2014 |
20140215419 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 07-31-2014 |
20140264772 | Shielding for Through-Silicon-Via - 3D integrated circuit devices include first and second semiconductor bodies. The first semiconductor body has an active area, a through-silicon-via outside the active area, and two or more disjoint guard rings. The first guard ring encircles the via. The second guard ring encircles the active area, but not the via. The guard rings can reduce the noise coupling coefficient between the via and the active area to −60 dB or less at 3 GHz and 20 μm spacing. | 09-18-2014 |
20140368264 | TEMPERATURE/VOLTAGE DETECTION CIRCUIT - A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal. | 12-18-2014 |
20140369381 | THERMAL SENSOR - A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value. Based on a second condition, the voltage node is configured to have a voltage decrease to the second voltage | 12-18-2014 |
20140372959 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 12-18-2014 |
20150035568 | TEMPERATURE DETECTOR AND CONTROLLING HEAT - A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET. | 02-05-2015 |