Patent application number | Description | Published |
20100165842 | Credit Management When Resource Granularity is Larger than Credit Granularity - In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes. | 07-01-2010 |
20110010502 | Cache Implementing Multiple Replacement Policies - In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy. | 01-13-2011 |
20110010504 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 01-13-2011 |
20110010520 | Block-Based Non-Transparent Cache - In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete. | 01-13-2011 |
20110010521 | TLB Prefetching - In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used. | 01-13-2011 |
20120008500 | Credit Management When Resource Granularity is Larger than Credit Granularity - In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes. | 01-12-2012 |
20120278557 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 11-01-2012 |
20130021072 | Dynamic Frequency Control Using Coarse Clock Gating - A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal. | 01-24-2013 |
20130021353 | Virtual GPU - Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs may allow for finer-grained execution control, and for better GPU efficiency. | 01-24-2013 |
20130151781 | Cache Implementing Multiple Replacement Policies - In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy. | 06-13-2013 |
20140025900 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 01-23-2014 |
20140059297 | SYSTEM CACHE WITH STICKY ALLOCATION - Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and each line allocated in the system cache may be associated with a specific group ID. Also, each line may have a corresponding sticky state which indicates if the line should be retained in the cache. The sticky state is determined by an allocation hint provided by the requesting agent. When a cache line is allocated with the sticky state, the line will not be replaced by other cache lines fetched by any other group IDs. | 02-27-2014 |
20140075118 | SYSTEM CACHE WITH QUOTA-BASED CONTROL - Methods and apparatuses for implementing a system cache with quota-based control. Quotas may be assigned on a group ID basis to each group ID that is assigned to use the system cache. The quota does not reserve space in the system cache, but rather the quota may be used within any way within the system cache. The quota may prevent a given group ID from consuming more than a desired amount of the system cache. Once a group ID's quota has been reached, no additional allocation will be permitted for that group ID. The total amount of allocated quota for all group IDs can exceed the size of system cache, such that the system cache can be oversubscribed. The sticky state can be used to prioritize data retention within the system cache when oversubscription is being used. | 03-13-2014 |
20140095800 | SYSTEM CACHE WITH STICKY REMOVAL ENGINE - Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID. | 04-03-2014 |
20140372699 | TRANSLATING CACHE HINTS - Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol. | 12-18-2014 |