Patent application number | Description | Published |
20110004938 | Method and Apparatus for Erasure of Data from a Data Storage Device Located on a Vehicle - A method and system for destroying information stored on a data storage device located onboard a vehicle in order to prevent unfriendly forces from obtaining the information is described. The method and system are initiated when the operator of the vehicle activates a triggering mechanism. The information may be destroyed by physically damaging the data storage device on which the information is stored or by releasing a software virus into the device on which the sensitive information is stored. A software virus may also be transmitted to a computer of an unfriendly force attempting to access the sensitive information. | 01-06-2011 |
20120068846 | TAMPER EVENT DETECTION - A tamper-indicating assembly includes a container formed by a plurality of walls and a door mechanically coupled to at least one of the walls via a hinge. At least one cable extends at least partially through the hinge between the door and the at least one wall. The cable transmits a signal, and the assembly can identify potential tamper events related to opening and closing of the door based on changes in properties of the transmitted signal. Techniques for forming the assembly are also described. | 03-22-2012 |
20120198242 | DATA PROTECTION WHEN A MONITOR DEVICE FAILS OR IS ATTACKED - In some examples, a system includes a data storage device that stores data and a monitor device that monitors a physical domain in which the data storage device is located and conditions access to data stored by the data storage device based on communication between the monitor device and the data storage device. In some examples, the system is configured to impede access to the data when at least one of operation the monitor device fails or the monitor device is attacked. Additionally, in some examples, the monitor device is configured to restrict access to the data when the monitor device is engaged and an attacker attempts to access the data storage device directly. | 08-02-2012 |
20120210138 | CRYPTOGRAPHIC LOGIC CIRCUIT WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS - This disclosure describes techniques that may prevent cryptographic devices, including both encryption devices and decryption devices, from producing a power signature that can be used by attackers to deconstruct a cryptographic algorithm and extract a cryptographic key. The techniques may include an external power supply charging an internal, dedicated power storage element; temporarily gating off the encryption device from the external power supply; configuring a cryptographic logic unit to perform a cryptographic algorithm from power stored in the power storage element while the external power source is gated off; and then recharging the power storage element upon the cryptographic logic unit completing an iteration of the cryptographic algorithm. | 08-16-2012 |
20130034329 | MODULAR OPTICAL ASSEMBLY - An assembly includes an optical device including an optical component and a plurality of supporting electrical components, a housing that is configured to house the optical component, a cap that is configured to substantially enclose the optical component in the housing, and a mounting member that is configured to removably electrically and mechanically connect the optical component to a printed board. In some examples, the housing does not house any electrical components of the optical device. The housing is physically separate from the mounting member and is configured to removably mechanically connect to the mounting member. The housing and mounting member define an electrically conductive pathway from the optical component to the printed board. When the cap is mechanically disconnected from the housing, the optical component may be exposed. The cap may also be configured to mechanically and optically connect an optical fiber assembly to the optical component. | 02-07-2013 |
20130145177 | MEMORY LOCATION SPECIFIC DATA ENCRYPTION KEY - Contents of a memory are encrypted using an encryption key that is generated based on a random number and a memory location at which the contents are stored. Each of a plurality of locations of a memory can be associated with a respective unique pointer value, and an encryption key may be generated based on the unique pointer value and the random number. In some examples, the random number is unique to a power-up cycle of a system comprising the memory or is generated based on a time at which the data to be stored by the memory at the selected memory location is written to the memory. | 06-06-2013 |
20130235544 | INTEGRATED CIRCUIT STACK - In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer. | 09-12-2013 |
20130241014 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) PACKAGE INCLUDING A MULTILAYER MAGNETIC SECURITY STRUCTURE - A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer. | 09-19-2013 |
20130242646 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIE INCLUDING AN INTEGRATED MAGNETIC SECURITY STRUCTURE - An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer. | 09-19-2013 |
20130250662 | TAMPER-RESISTANT MRAM UTILIZING CHEMICAL ALTERATION - A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir. | 09-26-2013 |
20130250663 | ANTI-TAMPERING DEVICES AND TECHNIQUES FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell. | 09-26-2013 |