Patent application number | Description | Published |
20090086871 | Apparatus for distributing a signal - An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal. | 04-02-2009 |
20090289700 | FORWARDED CLOCK FILTERING - Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed. | 11-26-2009 |
20090310728 | IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT - According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die. | 12-17-2009 |
20110161748 | Systems, methods, and apparatuses for hybrid memory - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 06-30-2011 |
20120284436 | SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 11-08-2012 |
20130283070 | HOST CONTROLLED IO POWER MANAGEMENT - Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output. | 10-24-2013 |
20140068135 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-06-2014 |
20140184270 | WIDTH SCALABLE CONNECTOR FOR HIGH BANDWIDTH IO INTERFACES - Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer. | 07-03-2014 |
20140197696 | INTERCHANGEABLE POWER AND SIGNAL CONTACTS FOR IO CONNECTORS - Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits. | 07-17-2014 |
20140208126 | RATE SCALABLE IO INTERFACE WITH ZERO STAND-BY POWER AND FAST START-UP - Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command. | 07-24-2014 |
20140237142 | BANDWIDTH CONFIGURABLE IO CONNECTOR - Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. | 08-21-2014 |
20140242927 | UNIVERSAL IO CONNECTOR AND INTERFACE CAPABLE OF BOTH WIRED AND WIRELESS OPERATION - Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts. | 08-28-2014 |
20140357128 | RATE SCALABLE CONNECTOR FOR HIGH BANDWIDTH CONSUMER APPLICATIONS - Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs. | 12-04-2014 |
20150089110 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-26-2015 |