Patent application number | Description | Published |
20120005473 | Secure Dynamically Reconfigurable Logic - A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic. | 01-05-2012 |
20120096084 | SHARED MEDIA EXPERIENCE DISTRIBUTION AND PLAYBACK - Embodiments of the present invention provide a method, system and computer program product for providing a shared user experience during media playback. In an embodiment of the invention, a method for providing a shared user experience during media playback is provided. The method includes selecting for a particular user a media file for playback in a media player executing in memory by a processor of a computer. The method also includes retrieving a shared user experience audio file recorded for a different user during a previous playback of the selected media file. Finally, the method includes playing back for the particular user both the selected media file and the retrieved shared user experience audio file concurrently in the media player. | 04-19-2012 |
20120216004 | THREAD TRANSITION MANAGEMENT - Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination. | 08-23-2012 |
20120284720 | HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM - Apparatus and methods for hardware assisted scheduling of software tasks in a computer system are disclosed. For example, a computer system comprises a first pool for maintaining a set of executable software threads, a first scheduler, a second pool for maintaining a set of active software threads, and a second scheduler. The first scheduler assigns a subset of the set of executable software threads to the set of active software threads and the second scheduler dispatches one or more threads from the set of active software threads to a set of hardware threads for execution. In one embodiment, the first scheduler is implemented as part of the operating system of the computer system, and the second scheduler is implemented in hardware. | 11-08-2012 |
20130290473 | REMOTE PROCESSING AND MEMORY UTILIZATION - According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message. | 10-31-2013 |
20140040592 | ACTIVE BUFFERED MEMORY - According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address. | 02-06-2014 |
20140047060 | REMOTE PROCESSING AND MEMORY UTILIZATION - According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message. | 02-13-2014 |
20140136811 | ACTIVE MEMORY DEVICE GATHER, SCATTER, AND FILTER - Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred. | 05-15-2014 |
20140149464 | TREE TRAVERSAL IN A MEMORY DEVICE - Embodiments relate to tree traversal in a memory device. An aspect includes a method for tree traversal in a memory device. The method includes receiving a pointer to a tree structure within memory of the memory device. An evaluation condition is received to identify a desired node of the tree structure. The tree structure is traversed to identify the desired node. Data is returned from the desired node meeting the evaluation condition. | 05-29-2014 |
20140258691 | THREAD TRANSITION MANAGEMENT - Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination. | 09-11-2014 |
20150032968 | IMPLEMENTING SELECTIVE CACHE INJECTION - A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element. | 01-29-2015 |