Patent application number | Description | Published |
20130140605 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 06-06-2013 |
20130146863 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 06-13-2013 |
20130157440 | Composite wafer for fabrication of semiconductor devices - A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate. | 06-20-2013 |
20130302972 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 11-14-2013 |
20140077266 | Heterostructure Transistor with Multiple Gate Dielectric Layers - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts. | 03-20-2014 |
20140124789 | GaN High Voltage HFET with Passivation Plus Gate Dielectric Multilayer Structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 05-08-2014 |
20140239309 | Heterostructure Power Transistor With AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 08-28-2014 |
20140374768 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 12-25-2014 |
20150076510 | Heterostructure Power Transistor with AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 03-19-2015 |