Patent application number | Description | Published |
20100289544 | Receiver With Enhanced Clock And Data Recovery - A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler. | 11-18-2010 |
20110304374 | METHODS AND APPARATUS FOR A GRAY-CODED PHASE ROTATING FREQUENCY DIVIDER - Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase based on one or more selection bits that are part of a selection input, and a gray code generator configured to generate a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single selector change. A method includes grouping a plurality of clock phases into two or more groups, for each group, selecting a respective clock phase based on one or more selection bits that are part of a selection input, and generating a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single group change. | 12-15-2011 |
20120083205 | NFC DEVICE HAVING A DIFFERENTIAL INPUT ENVELOPE DETECTOR - A differential input envelope detector receives an unamplified Near Field Communication (NFC) input signal from an NFC antenna and downconverts an NFC intelligence signal to baseband. In one example, the NFC input signal includes the NFC intelligence signal modulated onto a carrier. The differential input envelope detector downconverts and outputs the downconverted NFC intelligence signal onto an output node in such a way that the fundamental and odd harmonics of the carrier are canceled on the output node. There is substantially no signal of the frequency of the carrier present on the output node and this facilitates filtering of the downconverted NFC intelligence signal from interference and data recovery. An NFC data recovery circuit receives the downconverted NFC intelligence signal from the envelope detector output node. The NFC data recovery circuit can be a low power digital circuit involving an ultra-low power ADC and subsequent low power digital processing circuitry. | 04-05-2012 |
20120120992 | LO GENERATION AND DISTRIBUTION IN A MULTI-BAND TRANSCEIVER - A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE802.11a transmitter or receiver that transmits or receives in a second band. | 05-17-2012 |
20120242378 | FREQUENCY DIVIDER CIRCUIT - A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor. | 09-27-2012 |
20130106634 | NFC TRANSCEIVER | 05-02-2013 |
20130107913 | CLOCK AND DATA RECOVERY FOR NFC TRANSCEIVERS | 05-02-2013 |
20130109304 | ADAPTIVE SIGNAL SCALING IN NFC TRANSCEIVERS | 05-02-2013 |
20130109305 | ADAPTIVE NFC TRANSCEIVERS | 05-02-2013 |
20130109306 | NFC TRANSCEIVER UTILIZING COMMON CIRCUITRY FOR ACTIVE AND PASSIVE MODES | 05-02-2013 |
20140029143 | RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE - In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal. | 01-30-2014 |
20140029653 | LO GENERATION AND DISTRIBUTION IN A MULTI-BAND TRANSCEIVER - A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE 802.11a transmitter or receiver that transmits or receives in a second band. | 01-30-2014 |
20140091843 | PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS - A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit. | 04-03-2014 |