Patent application number | Description | Published |
20110312174 | Methods Of Manufacturing Three-Dimensional Semiconductor Devices - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 12-22-2011 |
20120098051 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded. | 04-26-2012 |
20140065810 | METHOD OF FORMING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded. | 03-06-2014 |
Patent application number | Description | Published |
20110316072 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ASYMMETRIC WORD LINE PADS - Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed. | 12-29-2011 |
20120119283 | METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion. | 05-17-2012 |
20120205722 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device. | 08-16-2012 |
20120299086 | SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed. | 11-29-2012 |
20140197470 | METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion. | 07-17-2014 |
20140231899 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 08-21-2014 |
20140367764 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts. | 12-18-2014 |
20150037949 | METHODS OF FORMING SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed. | 02-05-2015 |
20150255386 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES - A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns. | 09-10-2015 |
20150294980 | Semiconductor Memory Devices Including Fine Patterns and Methods of Fabricatring the Same - Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween. | 10-15-2015 |
20150303215 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 10-22-2015 |