Patent application number | Description | Published |
20090040826 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 02-12-2009 |
20090040830 | BLOCK DECODER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal. | 02-12-2009 |
20090052241 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node. | 02-26-2009 |
20090067254 | NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME - A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 03-12-2009 |
20090108916 | PUMP CIRCUIT - A pump circuit includes a plurality of transfer elements, capacitors, and controllers. The transfer elements are connected in series between a power supply terminal and an output terminal. The capacitors charge two terminals of each of the transfer elements according to first and second clock signals, respectively. Each of the controllers includes first and second switch elements, which are operated in opposite manners in response to the first or second clock signal to control each of the transfer elements. | 04-30-2009 |
20090141551 | METHOD FOR PERFORMING ERASING OPERATION IN NONVOLATILE MEMORY DEVICE - A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells. | 06-04-2009 |
20090231919 | SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME - A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder. | 09-17-2009 |
20090231927 | METHOD OF TESTING A NON-VOLATILE MEMORY DEVICE - A method of testing a non-volatile memory device on a wafer is disclosed. The method includes performing an erase operation and a first verify operation about every memory cell in the non-volatile memory device, storing data of a first latch in a page buffer for storing result in accordance with the first verify operation in a second latch, and setting the data of the first latch to data indicating pass of the verifying, and performing a soft program and a second verify operation about every memory cell. | 09-17-2009 |
20090290422 | METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes floating a drain select line, a source select line, a well, and a common source line of the nonvolatile memory device; precharging a program-inhibited bit line; and performing a program operation by applying a program voltage to a selected word line. The select lines and the well are floated to prevent the influence of a voltage applied to a bit line. Accordingly, degradation of the nonvolatile memory device can be prevented. | 11-26-2009 |
20100177565 | METHOD OF OPERATING A FLASH MEMORY DEVICE - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 07-15-2010 |
20100322004 | SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME - A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder. | 12-23-2010 |
20110026325 | METHOD OF PROGRAMMING A MULTI LEVEL CELL - A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 02-03-2011 |