Patent application number | Description | Published |
20090046462 | LAMP SOCKET, BACKLIGHT ASSEMBLY HAVING THE SAME, AND DISPLAY DEVICE HAVING THE SAME - A lamp socket includes a socket housing and a power supply member. The socket housing has a connecting hole. The power supply member includes a first lamp and a second lamp connecting terminal. The first lamp connecting terminal is inserted into the connecting hole, and includes a securing member for preventing a lamp from secession from the lamp socket. The second lamp connecting terminal is inserted into the connecting hole, and includes securing member opening inserted by the securing member. Therefore, the number of elements may be decreased and the stability of lamp socket may be increased. | 02-19-2009 |
20090140976 | DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - In a display apparatus, an interface unit receives N image signal groups each including i×j image signals from an external video system, wherein N is a natural number equal to or greater than 2. A display panel includes data lines, gate lines, and pixels to display images. The display panel includes N display areas each having a resolution of i×j, and the N display areas are extended along a vertical direction and sequentially arranged along a horizontal direction. The N display areas display the images corresponding to the N image signal groups input through the N interface units, respectively. Thus, although the display apparatus has an ultra high-definition resolution, a frequency for transmission of the image signals may be prevented from being increased, so that no additional memories are required. | 06-04-2009 |
20090322661 | DISPLAY APPARATUS - A display apparatus includes a plurality of frame rate controllers that generate a motion interpolated intermediate image. The frame rate controllers exchange image information with adjacent frame rate controllers. According to the display apparatus, each frame rate controller displays the intermediate image on a corresponding display area based on the image information provided from the adjacent frame rate controller. | 12-31-2009 |
20100128024 | METHOD OF DRIVING A LIGHT SOURCE, DISPLAY APPARATUS FOR PERFORMING THE METHOD AND METHOD OF DRIVING THE DISPLAY APPARATUS - In method of individually driving a plurality of light-emitting blocks of a light source module providing light to a display panel including a unit pixel, luminance of a first light-emitting block corresponding to a first image block that includes an out of gamut (OOG) data among a plurality of image blocks corresponding to the light-emitting blocks is boosted. A second light-emitting block corresponding to a second image block that does not include the OOG data is driven so that the second light-emitting block has luminance corresponding to a representative gray-scale of the second image block. | 05-27-2010 |
20110175865 | DISPLAY APPARATUS - A display apparatus includes a plurality of frame rate controllers that generate a motion interpolated intermediate image. The frame rate controllers exchange image information with adjacent frame rate controllers. According to the display apparatus, each frame rate controller displays the intermediate image on a corresponding display area based on the image information provided from the adjacent frame rate controller. | 07-21-2011 |
Patent application number | Description | Published |
20100303436 | VIDEO PROCESSING SYSTEM, VIDEO PROCESSING METHOD, AND VIDEO TRANSFER METHOD - A video processing system is provided. The video processing system includes: a camera that compresses a captured video and provides the compressed video; a video preparation unit including a playback server that decodes a moving picture compression stream transmitted from the camera and a video processor that processes a video decoded by the playback server; and a display device that displays a video prepared and provided by the video preparation unit. Accordingly, a video captured and compressed by a camera is prepared by decoding, and the video is configured with various output conditions so as to be displayed on a display device. This, in comparison with the convention method in which a required video is decoded and displayed whenever a video display condition changes, the required video can be rapidly displayed within a short period of time, and videos captured by a plurality of cameras can be displayed on one image on a real time basis while maintaining a maximum frame rate of the cameras without restriction of the number of cameras. Therefore, there is an advantage in that a specific video can be zoomed in, zoomed out, or panned on a real time basis at the request of a user, thereby improving a usage rate and an operation response of the video processing system. | 12-02-2010 |
20130279871 | VIDEO PROCESSING SYSTEM AND VIDEO PROCESSING METHOD - A video processing system includes: a merge server configured to decode a plurality of individual videos provided from video providing units, encode the plurality of individual videos by adjusting an amount of data of each of the individual videos to generate a preliminary video, and provide the preliminary video; a display server configured to receive the preliminary video and configure final videos according to output conditions of a display device; and a control server configured to receive the output conditions from the display server and transfer an output control signal with respect to the preliminary video to the merge server. When a user wants, individual videos provided from the plurality of video providing units can be displayed on a display device without sacrificing resolution and a frame rate, and since videos can be zoomed in/out and panned in real time, operational responsiveness and usage efficiency of the video processing system can be enhanced. | 10-24-2013 |
Patent application number | Description | Published |
20130193820 | THERMAL INSULATION PERFORMANCE MEASUREMENT APPARATUS AND MEASUREMENT METHOD USING THE SAME - A thermal insulation performance measurement apparatus which measures thermal insulation performance of a thermal insulator by heat flux to the thermal insulator, measured by a heat flux sensor, and a measurement method using the same includes a heat flux sensor provided with one surface adapted to contact an object to be measured, a first heat source arranged on the upper surface of the heat flux sensor to supply heat to the heat flux sensor, a thermal insulator arranged on the upper surface of the first heat source, a third heat source arranged on the upper surface of the thermal insulator, and a second heat source arranged around the heat flux sensor. | 08-01-2013 |
20140050246 | THERMAL INSULATION PERFORMANCE MEASUREMENT APPARATUS AND MEASUREMENT METHOD USING THE SAME - A thermal insulation performance measurement apparatus which measures thermal insulation performance of a thermal insulator by heat flux to the thermal insulator, measured by a heat flux sensor, and a measurement method using the same includes a heat flux sensor provided with one surface adapted to contact an object to be measured, a first heat source arranged on the upper surface of the heat flux sensor to supply heat to the heat flux sensor, a thermal insulator arranged on the upper surface of the first heat source, a third heat source arranged on the upper surface of the thermal insulator, and a second heat source arranged around the heat flux sensor. | 02-20-2014 |
20160061490 | Cooking Appliance - Provided is a cooking appliance having an improved structure in which superheated steam is capable of being used during a cooking operation. The cooking appliance supplies superheated steam while food is cooked, and includes: a main body, a front of which is opened and in which a cooking compartment is disposed; a heating chamber disposed in the main body to be in communication with the cooking compartment; a steam generator disposed to generate steam sprayed into the heating chamber; and a convection heater disposed in the heating chamber to heat the heating chamber and the cooking compartment. The convection heater heats steam discharged from the steam generator, and the steam discharged from the steam generator, in a superheated steam state, is sprayed into the heating chamber and supplied into the cooking compartment. | 03-03-2016 |
Patent application number | Description | Published |
20100072598 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 03-25-2010 |
20100117200 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING A REINFORCING MEMBER THAT PREVENTS DISTORTIONS AND METHOD FOR FABRICATING THE SAME - A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body. | 05-13-2010 |
20130026651 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 01-31-2013 |
20140332946 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 11-13-2014 |
Patent application number | Description | Published |
20100060491 | Operating apparatus and electronic device having the same - Disclosed herein are an operating apparatus and an electronic device having the same. According to the operating apparatus, key values of a button can be variably changed each time a key value changing button is pushed so that the button can have several key values. Accordingly, a variety of functions of the electronic device can be achieved although the total number of the buttons is reduced. | 03-11-2010 |
20150016017 | DIELECTRIC COMPOSITION AND MULTI-LAYERED CERAMIC CAPACITOR - A dielectric composition may include a first dielectric powder; and a second dielectric powder having an average grain size smaller than that of the first dielectric powder and included in the dielectric composition in an amount of 0.01 to 1.5 parts by weight based on 100 parts by weight of the first dielectric powder, and a multilayer ceramic capacitor formed using the same. A multilayer ceramic capacitor may include: a ceramic body including dielectric layers; first and second internal electrodes disposed in the ceramic body to face each other with the respective dielectric layers interposed therebetween; and first and second external electrodes electrically connected to the first and second internal electrodes, respectively. The dielectric layers are formed of a dielectric composition including a first dielectric powder and a second dielectric powder having an average grain size smaller than that of the first dielectric powder and included in the dielectric composition in an amount of 0.01 to 1.5 parts by weight based on 100 parts by weight of the first dielectric powder. | 01-15-2015 |
20150162132 | MULTILAYER CERAMIC ELECTRONIC PART AND BOARD HAVING THE SAME MOUNTED THEREON - There is provided a multilayer ceramic electronic part including: a ceramic body including dielectric layers; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body; upper and lower cover layers formed on upper and lower portions of the active layer; and first and second external electrodes formed on both end portions of the ceramic body, wherein the first external electrode includes a first base electrode, a first conductive layer formed on the first base electrode at a corner portion of the ceramic body, and the second external electrode includes a second base electrode, a second conductive layer formed on the second base electrode at a corner portion of the ceramic body, the first and second conductive layers being positioned outside the active layer in a thickness direction of the ceramic body. | 06-11-2015 |
20150299046 | DIELECTRIC CERAMIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR CONTAINING THE SAME - A dielectric ceramic composition may include a base powder represented by (1−x)BaTiO | 10-22-2015 |
20150299047 | DIELECTRIC CERAMIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR CONTAINING THE SAME - A dielectric ceramic composition may include a base powder represented by (1−a)[(1−x)BaTiO | 10-22-2015 |
20160002111 | DIELECTRIC CERAMIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR INCLUDING THE SAME - A dielectric ceramic composition may include a base material main ingredient and an accessory ingredient. The accessory ingredient contains one or more selected from a group consisting of oxides and carbonates of one or more elements among Bi, Li, and Cu. When the accessory ingredient contains Bi, a content of Bi may be 0.1 to 1.0 part by mole, based on 100 parts by mole of the base material main ingredient, when the accessory ingredient contains Li, a content of Li may be 0.1 to 1.0 part by mole, based on 100 parts by mole of the base material main ingredient, and when the accessory ingredient contains Cu, a content of Cu may be 0.1 to 1.0 part by mole, based on 100 parts by mole of the base material main ingredient. | 01-07-2016 |
20160086735 | DIELECTRIC CERAMIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR COMPRISING THE SAME - There are provided a dielectric ceramic composition comprising ceramic dielectrics and a multilayer ceramic capacitor including the same. The dielectrics have grains of a core-shell structure, and when a diameter of a core is defined as D | 03-24-2016 |
Patent application number | Description | Published |
20120307417 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component including: a lamination main body including a dielectric layer; and a plurality of inner electrode layers formed within the lamination main body and having ends exposed from one or more faces of the laminated main body, wherein when a distance between central portions of adjacent inner electrodes among the plurality of inner electrodes is T | 12-06-2012 |
20120307418 | MULTILAYER CERAMIC CAPACITOR - There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t | 12-06-2012 |
20130070386 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component including a lamination main body including a plurality of inner electrodes. When T | 03-21-2013 |
20130100578 | MULTILAYER CERAMIC ELECTRONIC PART - There is provided a multilayer ceramic electronic part, including: a ceramic body having a plurality of dielectric layers laminated therein; a plurality of inner electrode layers formed on at least one surface of each dielectric layer; and margin dielectric layers formed on a margin part of each dielectric layer, on which the inner electrode layers are not formed, and having a dielectric grain size smaller than that of the dielectric layers. | 04-25-2013 |
20130114182 | MULTILAYER CERAMIC CAPACITOR - There is provided a multilayer ceramic capacitor, including: a ceramic element having a plurality of dielectric layers stacked therein; a plurality of inner electrode layers formed on each dielectric layer; margin dielectric layers each formed on a margin part of each dielectric layer, on which the inner electrode layers are not formed, the margin dielectric layers having a porosity of 10% or less; and outer electrodes formed on outer surfaces of the ceramic element. | 05-09-2013 |
20140071586 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic body; and first and second external electrodes formed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, wherein, when the dielectric layer is divided into three areas in a thickness direction of the ceramic body, an average size of dielectric grains in a middle area is different from that of dielectric grains in upper and lower areas, and when T | 03-13-2014 |
20140092522 | MULTILAYER CERAMIC CAPACITOR - There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10. | 04-03-2014 |
20140098457 | DIELECTRIC COMPOSITION AND MULTILAYER CERAMIC ELECTRONIC COMPONENT MANUFACTURED USING THE SAME - There are provided a dielectric composition and a multilayer ceramic electronic component manufactured using the same, the dielectric composition including a dielectric grain having a perovskite structure represented by ABO | 04-10-2014 |
20140185183 | DIELECTRIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR USING THE SAME - There is provided a multilayer ceramic capacitor, including: a ceramic body including dielectric layers; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic body; a first external electrode electrically connected to the first internal electrodes; and a second external electrode electrically connected to the second internal electrodes, wherein the dielectric layer includes 40 to 99 wt % of barium titanate (BaTiO | 07-03-2014 |
Patent application number | Description | Published |
20090184783 | RESONANT STRUCTURE COMPRISING WIRE, RESONANT TUNNELING TRANSISTOR, AND METHOD FOR FABRICATING THE RESONANT STRUCTURE - A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced. | 07-23-2009 |
20090267706 | RESONATOR AND FABRICATION METHOD THEREOF - A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level. | 10-29-2009 |
20100244113 | MOS VARACTOR AND FABRICATING METHOD OF THE SAME - The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t109-30-2010 | |
20110084766 | WIDEBAND ACTIVE CIRCUIT WITH FEEDBACK STRUCTURE - A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit. | 04-14-2011 |
20120126327 | RESONATOR HAVING TERMINALS AND A METHOD FOR MANUFACTURING THE RESONATOR - A resonator and a method for manufacturing a resonator are provided. The method may include doping a wafer, and forming on the wafer a substrate, a drain electrode, a source electrode, a gate electrode, and at least one nanowire. | 05-24-2012 |
20140077897 | RESONATOR AND FABRICATION METHOD THEREOF - A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level. | 03-20-2014 |
20140110763 | NANO RESONANCE APPARATUS AND METHOD - A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode. | 04-24-2014 |
20140191185 | APPARATUS AND METHOD FOR FABRICATING NANO RESONATOR USING LASER INTERFERENCE LITHOGRAPHY - A method of fabricating a nano resonator, includes forming a line pattern in a first substrate, and transferring the line pattern to a second substrate including a gate electrode. The method further includes forming a source electrode and a drain electrode on the transferred line pattern. | 07-10-2014 |
Patent application number | Description | Published |
20130264371 | Medical Anastomosis Apparatus - A medical anastomosis apparatus is provided. The medical anastomosis apparatus includes a cylindrical body which has a hollow portion and extends in a longitudinal direction, a pressing rod which is provided inside of the hollow portion of the body to translate along the hollow portion, a knob which is coupled to the pressing rod to provide a driving force to translate the pressing rod, a guide member which is inserted into one end of the body and simultaneously coupled to expose a portion of the body and has a pressing unit formed therein to move radially upon translation of the pressing rod, and a staple cartridge which is inserted around an outer circumferential surface of the guide member and then coupled to the body and has built-in staple clips that protrude outward upon movement of the pressing unit. | 10-10-2013 |
20140313410 | System And Method For Controlling Motion Using Time Synchronization Between Picture And Motion - Provided are a system and a method for controlling a motion using time synchronization between a picture and the motion, and more particularly, a motion code corresponding to a time code is prestored before showing the picture and the motion is controlled according to the prestored motion code when the picture showing starts while a current motion driving time is compared with a reference time of the picture and then synchronized to provide a high-resolution precision motion to a user while achieving accurate synchronization with the picture. | 10-23-2014 |
20140318029 | System For Controlling Seat Effect For Facility Of Showing Pictures - Provided is a system for controlling a seat effect for a facility of showing pictures, and particularly, a user on a rear line may easily and safely control an effect provided to the user himself/herself even while a seat is in motion operation at the time of showing pictures by controlling an effect synchronized with pictures by relaying control information inputted from the user on the rear-line seat by using an effect controlling device of a front-line seat, in the facility of showing pictures, which provides the effect (for example, a water shot, an air shot, or a scent) synchronized with the pictures to the user on the rear-line seat. | 10-30-2014 |
Patent application number | Description | Published |
20110177639 | METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor pattern formed over the gate insulation layer; data wiring formed over the gate insulation layer or the semiconductor pattern and including source electrodes, drain electrodes, and data pads; a protection layer including a Nega-PR type of organic insulating layer formed all over the semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel electrode connected to the drain electrode. When exposing the Nega-PR type of passivation layer in the pad region during a photolithography process, a photomask having a lattice pattern made of a metal such as Cr that has a line width of less than the resolution of a light exposer is used. Thus, the resulting post-etch height of the passivation layer can be selectively controlled so as to provide reduced effective thickness in the pad regions. | 07-21-2011 |
20110254815 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the drain electrode, forming a negative photosensitive organic layer on the passivation layer, heat treating the negative photosensitive organic layer to form an insulating layer including a first portion, and a second portion that is thinner than the first portion, and forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer. The pixel electrode is disposed on the first portion, the first and second contact assistants are disposed on the second portion, and the thickness of the second portion is less than about 1.5 micrometers (μm). | 10-20-2011 |
20120154722 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL HAVING THE SAME - A display panel includes a base substrate having a plurality of pixel areas, in which each pixel area includes a plurality of sub-pixel areas, a light blocking layer pattern generally defining the sub-pixel areas, and a plurality of color filter patterns. Upper surfaces of the light blocking layer pattern and the plurality of color filter patterns collectively form a generally flat surface. | 06-21-2012 |
20130075736 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes: an substrate; a gate line and a gate pad portion disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad portion; a data line and a data pad portion disposed on the gate insulating layer; a gate assistance pad portion disposed at a position corresponding to the gate pad portion; a first insulating layer disposed on the data line and removed at the gate pad portion and the data pad portion; a first field generating electrode disposed on the first insulating layer; a second insulating layer disposed on the first field generating electrode and removed at the gate pad portion and the data pad portion; and a second field generating electrode disposed on the second insulating layer. The assistance gate pad portion and the gate insulating layer include a contact hole exposing the gate pad portion. | 03-28-2013 |
20130140570 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes an insulation substrate; a gate line on the insulation substrate; a gate insulating layer on the gate line; a data line on the gate insulating layer; a first insulating layer on the data line and including a first contact hole which exposes a portion of the data line; a first connection assistant member in the first contact hole; and further including a first field generating electrode on the first insulating layer. The first field generating electrode is in connection with the exposed portion of the data line through the first connection assistant member. | 06-06-2013 |
20130240889 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the drain electrode, forming a negative photosensitive organic layer on the passivation layer, heat treating the negative photosensitive organic layer to form an insulating layer including a first portion, and a second portion that is thinner than the first portion, and forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer. The pixel electrode is disposed on the first portion, the first and second contact assistants are disposed on the second portion, and the thickness of the second portion is less than about 1.5 micrometers (μm). | 09-19-2013 |
20140140153 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not. | 05-22-2014 |
20140176893 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device according to an exemplary embodiment of the present invention includes a substrate including a plurality of pixel regions, a thin film transistor disposed on the substrate, and a pixel electrode connected to the thin film transistor and disposed in a first pixel region. A roof layer is disposed on the pixel electrode and spaced apart from the pixel electrode with a microcavity interposed therebetween. The plurality of pixel regions is disposed in a matrix form including a plurality of pixel rows and a plurality of pixel columns, the roof layer is disposed along the plurality of pixel rows, and the roof layer includes a bridge portion connecting the roof layers disposed in different pixel rows. | 06-26-2014 |
20140183162 | PHOTORESIST COMPOSITION AND METHOD FOR FORMING A METAL PATTERN - A method of forming a metal pattern is disclosed. In the method, a metal layer is formed on a base substrate. A photoresist composition is coated on the metal layer to form a coating layer. The photoresist composition includes a binder resin, a photo-sensitizer and a mixed solvent including a first solvent, a second solvent having a higher volatility than the first solvent, and a third solvent having a higher volatility than the second solvent. The coating layer is exposed to light. The coating layer is partially removed to form a photoresist pattern. The metal layer is patterned by using the photoresist pattern as a mask. | 07-03-2014 |
20140241093 | DEVICES, SYSTEMS AND METHODS WITH IMPROVED REFRESH ADDRESS GENERATION - A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation. | 08-28-2014 |
20140327866 | PHOTOSENSITIVE RESIN COMPOSITION, METHOD OF FORMING PATTERN, AND LIQUID CRYSTAL DISPLAY USING THE SAME - A photosensitive resin composition is disclosed. The disclosed photosensitive resin composition includes an acryl-based copolymer formed by copolymerizing i) unsaturated carboxylic acid, unsaturated carboxylic acid anhydride, or a mixture thereof, and ii) an olefin-based unsaturated compound or a mixture thereof, a dissolution inhibitor in which a phenolic hydroxyl group is protected by an acid-degradable acetal or ketal group, a photoacid generator, and a solvent. | 11-06-2014 |
20150091011 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device and a method for fabricating a display device are provided. According to one embodiment of the present invention, a display device includes a substrate, an insulating layer arranged on the substrate, a wiring pattern arranged on the insulating layer, an organic layer arranged on the wiring pattern, and a contact hole penetrating the organic layer to expose at least a portion of the wiring pattern. The side wall of the organic layer that defines the contact hole includes a first side wall portion and a second side wall portion, and a value obtained by dividing a vertical distance of the first side wall portion by a horizontal distance of the first side wall portion is different from a value obtained by dividing a vertical distance of the second side wall portion by a horizontal distance of the second side wall portion. | 04-02-2015 |
Patent application number | Description | Published |
20100272949 | VACUUM INSULATOR - A vacuum insulator includes first lateral beams, first longitudinal beams, second lateral beams and second longitudinal beams. The first longitudinal beams are arranged in parallel to one another at a predetermined interval. Each of the first lateral beams has a sectional area alternatively changed to be wide and narrow by the period that is ½ of the interval. The first longitudinal beams are intersected with the first lateral beams at a predetermined angle, and are arranged in parallel to one another at a predetermined interval. Each of the first longitudinal beams has a sectional area alternatively changed to be wide and narrow by the period that is ½ of the interval. Portions with the wide sectional area of each of the first longitudinal beams are attached on portions with the wide sectional area of each of the first lateral beam. The second lateral beams are intersected with the first longitudinal beams, and are arranged in parallel to one another at a predetermined interval at a predetermined angle and are alternately positioned. Each of the second lateral beams has a sectional area alternatively changed to be wide and narrow by the period that is ½ of the interval. Portions with the wide sectional area of each of the second lateral beams are attached on portions with the wide sectional area of each of the first longitudinal beams. The second longitudinal beams are intersected with the second lateral beams at a predetermined angle and are arranged in parallel to one another at a predetermined interval to be alternately positioned with the first longitudinal beams. Each of the second longitudinal beams has a sectional area alternatively changed to be wide and narrow by the period that is ½ of the interval. Portions with the wide sectional area of each of the second longitudinal beams are attached on portions with the wide sectional area of each of the second lateral beams. | 10-28-2010 |
20100279055 | VACUUM INSULATOR - The vacuum insulator includes an internal structure; a filler for filling empty spaces of the internal structure; and an envelope having an upper envelope composed of a metal layer and a polymer layer formed on the metal layer to surround an upper surface of the internal structure, and a lower envelope composed of a metal layer and a polymer layer formed on the metal layer to surround a lower surface of the internal structure, the metal layer of the upper envelope and the metal layer of the lower envelope being opposite to each other, wherein in a certain area along outlines of the upper envelope and the lower envelope, the metal layer of the upper envelope and the metal layer of the lower envelope between which a film composed of a Low density polyethylene LDPE and a Linear-Lowdensity polyethylene LLDPE is inserted, are adhered by heat, and in an area excluding the certain area, the metal layer of the upper envelope and the metal layer of the lower envelope are adhered by polyurethane. | 11-04-2010 |
20120148786 | VACUUM INSULATOR - The vacuum insulator includes an internal structure; a filler for filling empty spaces of the internal structure; and an envelope having an upper envelope composed of a metal layer and a polymer layer formed on the metal layer to surround an upper surface of the internal structure, and a lower envelope composed of a metal layer and a polymer layer formed on the metal layer to surround a lower surface of the internal structure, wherein the metal layer of the upper envelope and the metal layer of the lower envelope being opposite to each other, wherein at an area facing the internal structure in an end of the envelope, the upper envelope and the lower envelope are adhered by a heat adhesion part, and at an area opposite to the internal structure in the end of the envelope, the upper envelope and the lower envelope are adhered by polyurethane. | 06-14-2012 |
20150346283 | APPARATUS AND METHOD FOR CALCULATING PRECHARGE RESISTANCE OF BATTERY PACK - Disclosed are an apparatus and a method for calculating a precharge resistance of a battery pack. The apparatus for calculating a precharge resistance of a battery pack according to the present invention includes: a load resistor configured to be connected between a battery pack and a precharge resistor in series; a voltage measuring unit configured to measure a no-load voltage in a no-load state in which the load resistor is not installed in the battery pack or a load voltage applied to the load resistor when the load resistor has a predetermined current value in a load state in which the load resistor is installed in the battery pack; and a precharge resistance calculating unit configured to calculate the precharge resistor of the battery pack using the no-load voltage of the battery pack, the load voltage, and the predetermined current value. | 12-03-2015 |
Patent application number | Description | Published |
20150076683 | Integrated Circuit Device Packages And Methods for Manufacturing Integrated Circuit Device Packages - An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device. | 03-19-2015 |
20150319843 | Memory Card Systems Comprising Flexible Integrated Circuit Element Packages, and Methods for Manufacturing Said Memory Card Systems - A memory card system may include a flexible integrated circuit device package, an upper flexible case, a lower flexible case, a wiring structure, an anisotropic conductive film, etc. The flexible integrated circuit device package may include a material capable of being bent or folded and a flexible integrated circuit device having a connection pad for an electrical connection. The upper flexible case may include a material capable of being bent or folded and may cover the integrated circuit device package. The lower flexible case may include a material capable of being bent or folded and the flexible integrated circuit device package may be fixed to the lower flexible case. The wiring structure may include a material capable of being bent or folded, and also may include a connection wiring disposed on an inner surface of the upper flexible case for electrically connecting the flexible integrated circuit device package with an external device, a connection pin disposed on an outer surface of the upper flexible case, and a via wiring passing through the upper flexible case. The anisotropic conductive film may be disposed between the flexible integrated circuit device package and the upper flexible case for electrically connecting the connection pad with the connection wiring. | 11-05-2015 |