Patent application number | Description | Published |
20080221953 | Sentient Optimization for Continuous Supply Chain Management - A system and method is disclosed for incrementally adjusting a supply chain plan. The system includes a database operable to store data associated with one or more supply chain entities and a server system coupled with the database. The server system receives one or more perturbations in supply chain plan inputs from one or more of the supply chain entities, wherein the perturbations are received during a period of time separating a supply chain planning session from a subsequent supply chain planning session and accesses the data stored in the database associated with the one or more supply chain entities. The server system also incrementally and optimally adjusts the supply chain plan based on the one or more received perturbations and the data stored in the database and communicates the incrementally adjusted supply chain plan to the one or more supply chain entities. | 09-11-2008 |
20100114667 | Fast Planning Heuristic for Batch and Interactive Planning - A system and method is disclosed for incremental planning using a list based heuristic. The system includes a database storing supply chain entity data and a server system coupled with the database. The server system receives demand for one or more end items from one or more of the supply chain entities within a supply chain network and collapses the supply chain network into one or more flowpaths for each of the one or more end items. The server system also sorts the one or more flowpaths based on one or more rules or parameters stored in the database and reduces the one or more flowpaths using constraints stored in the database. The server system further generates a supply chain plan by solving the received demand using a list based heuristic stored in the database and communicates the generated supply chain plan to the one or more supply chain entities. | 05-06-2010 |
20120265581 | System and Method for Multi-Enterprise Supply Chain Optimization - A method of optimizing multi-enterprise supply chain agreements using an electronic scenario based option contract includes creating at a buyer computer a plurality of scenarios of forecasted demand for one or more products and communicating from the buyer computer to a seller computer an offer to enter into an option contract for the supply of the one or more products, the option contract including an option corresponding to each of the plurality of scenarios of forecasted demand. The method further includes executing the option contract, receiving at the buyer computer an indication of current buyer demand for at least one scenario associated with the one or more products, and exercising at least a portion of the option in the option contract based at least in part on the indicated buyer demand. | 10-18-2012 |
20140046467 | Continuous Production Planning Using a Transition Matrix - A method for continuous production planning includes identifying a forbidden transition associated with production of first and second end products. The forbidden transition indicates that a manufacturer should not produce the first and second end products consecutively. The method also includes identifying a bridge product associated with the forbidden transition. The bridge product represents a product that the manufacturer could produce between production of the first and second end products. The method further includes determining a quantity of the bridge product that could be produced by the manufacturer. In addition, the method includes scheduling production of the first and second end products and the bridge product. At least a portion of the quantity of the bridge product is scheduled for production between the production of the first and second end products. | 02-13-2014 |
Patent application number | Description | Published |
20110229400 | PROCESS FOR PRODUCING HYDROGEN - A process is described for producing hydrogen comprising producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; and contacting the reformer feed stream with a hydrocarbon stream and a catalyst in a reformer under reforming conditions to produce a reformer product stream comprising hydrogen. | 09-22-2011 |
20110229404 | PROCESS FOR PRODUCING HYDROGEN - A process is described for producing hydrogen comprising producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; separating at least a portion of the water from the feed stream so that the concentration of ethanol in the resulting reformer feed stream is in the range of from 15% to 35% wt.; and contacting the reformer feed stream with a catalyst in a reformer under reforming conditions to produce a reformer product stream comprising hydrogen wherein the pressure in the reformer is in a range of from 100 psi to 600 psi. | 09-22-2011 |
20110229405 | PROCESS FOR PRODUCING HYDROGEN - A process is described for producing hydrogen comprising producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; separating at least a portion of the water from the feed stream so that the concentration of ethanol in the resulting reformer feed stream is in the range of from 15% to 35% wt.; and contacting the reformer feed stream with a catalyst in a reformer under steam reforming conditions to produce a reformer product stream comprising hydrogen wherein substantially no oxygen is added to the reformer. | 09-22-2011 |
20110301394 | PROCESS FOR THE CONVERSION OF LOWER ALKANES TO AROMATIC HYDROCARBONS - A process is provided for producing aromatic hydrocarbons which comprises: (a) contacting a lower alkane feed with a solid particulate aromatic hydrocarbon conversion catalyst in a fixed bed reaction zone to produce aromatic hydrocarbons and other products, whereby the catalyst is at least partially deactivated by the formation of undesirable coke deposits, (b) periodically regenerating the catalyst under regeneration conditions, (c) separating aromatic hydrocarbons from the other products and unreacted lower alkanes, and (d) optionally recycling unreacted lower alkanes to the reaction zone wherein the fixed bed reaction zone additionally comprises a volume of a catalytically inactive solid. | 12-08-2011 |
20110305627 | PROCESSES FOR HYDROGEN PRODUCTION AND CATALYSTS FOR USE THEREIN - This invention describes a process for producing hydrogen comprising: introducing a feedstream comprising a bio-based feedstock and water into a reformer and supplying heat to the reformer; contacting the feedstream with a steam reforming catalyst disposed within the reformer to form a reformate comprising hydrogen and carbon monoxide; recovering the reformate from the reformer; contacting the reformate with steam in the presence of a water-gas shift catalyst disposed within a water-gas shift reaction zone to form a water-gas shift product stream comprising hydrogen, and the water-gas shift product stream comprises hydrogen in a greater quantity than in the reformate; heating the feedstream by heat exchange contact of the feedstream with a product stream selected from the reformate, the water-gas shift product stream or combinations thereof to transfer heat from the product stream to the feedstream prior to introducing the feedstream into the reformer. | 12-15-2011 |
20120029256 | PROCESS FOR THE CONVERSION OF LOWER ALKANES TO AROMATIC HYDROCARBONS - A process is provided for producing aromatic hydrocarbons which comprises: (a) contacting a lower alkane feed with a solid particulate aromatic hydrocarbon conversion catalyst in a fluidized bed reaction zone to produce aromatic hydrocarbons and other products, whereby the catalyst is at least partly deactivated by the formation of undesirable coke deposits, (b) continuously withdrawing a portion of the catalyst from the reaction zone, regenerating it in a regeneration zone and returning regenerated catalyst to the reaction zone, (c) maintaining the heat balance between the reaction zone and the regeneration zone by diluting the catalyst particles with particles of a catalytically inactive solid with about the same or improved specific heat and thermal conductivity relative to the catalyst, (d) separating aromatic hydrocarbons from the other products and unreacted lower alkanes, and (e) optionally recycling unreacted lower alkanes to the reaction zone. | 02-02-2012 |
20120240467 | PROCESS FOR THE CONVERSION OF MIXED LOWER ALKANES TO AROMATIC HYDROCARBONS - A process for the conversion of mixed lower alkanes into aromatics which comprises first reacting a mixed lower alkane feed comprising at least propane and ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane into first stage aromatic reaction products, separating ethane from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products. | 09-27-2012 |
20120253089 | PROCESS FOR THE CONVERSION OF LOWER ALKANES TO AROMATIC HYDROCARBONS - The present invention provides a process for producing aromatic hydrocarbons which comprises: (a) alternately contacting a lower alkane feed with an aromatization catalyst under aromatization reaction conditions in a reactor for a short period of time, preferably 30 minutes or less, to produce aromatic reaction products and then contacting the aromatization catalyst with a hydrogen-containing gas at elevated temperature for a short period of time, preferably 10 minutes or less, (b) repeating the cycle of step (a) at least one time, (c) regenerating the aromatization catalyst by contacting it with an oxygen-containing gas at elevated temperature and (d) repeating steps (a) through (c) at least one time. | 10-04-2012 |
20120277089 | PROCESS FOR THE REGENERATION OF HYDROCARBON CONVERSION CATALYSTS - The present invention provides a process for hydrocarbon conversion, especially for producing aromatic hydrocarbons, which comprises: (a) alternately contacting a hydrocarbon feed, especially a lower alkane feed, with a hydrocarbon conversion catalyst, especially an aromatization catalyst, under hydrocarbon conversion, especially aromatization reaction conditions, in a reactor for a short period of time, preferably 30 minutes or less, to produce reaction products and then contacting the catalyst with hydrogen-containing gas at elevated temperature for a short period of time, preferably 10 minutes or less, (b) repeating the cycle of step (a) at least one time, (c) regenerating the catalyst by contacting it with an oxygen-containing gas at elevated temperature and (d) repeating steps (a) through (c) at least one time. | 11-01-2012 |
20130131414 | PROCESS FOR THE CONVERSION OF PROPANE AND BUTANE TO AROMATIC HYDROCARBONS - A process for the conversion of propane and/or butane into aromatics which comprises first reacting a propane and/or butane feed in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane and/or butane into first stage aromatic reaction products, separating ethane produced in the first stage reaction from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products. | 05-23-2013 |
Patent application number | Description | Published |
20130191431 | EFFICIENT FIR FILTERS - A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution. | 07-25-2013 |
20130262819 | SINGLE CYCLE COMPARE AND SELECT OPERATIONS - An apparatus includes a processor to determine an extremum among a series of values that are successively provided to a first register and a second register. The processor is configured to execute a single cycle search instruction, including compare a value in the first register with a value in a first accumulator, and store an extremum of the two values in the first accumulator; and compare a value in the second register with a value in a second accumulator, and store an extremum of the two values in the second accumulator. The processor is configured to execute a single cycle select instruction, including compare the value in the first accumulator with the value in the second accumulator, and store an extremum of the two values in the first accumulator, the extremum stored in the first accumulator representing the extremum of the series of numbers. | 10-03-2013 |
20140129807 | APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS - A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations. | 05-08-2014 |
20140143564 | APPROACH TO POWER REDUCTION IN FLOATING-POINT OPERATIONS - An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit. | 05-22-2014 |
20140351308 | SYSTEM AND METHOD FOR DYNAMICALLY REDUCING POWER CONSUMPTION OF FLOATING-POINT LOGIC - A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output. | 11-27-2014 |
20150039662 | FFMA OPERATIONS USING A MULTI-STEP APPROACH TO DATA SHIFTING - A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product. | 02-05-2015 |
Patent application number | Description | Published |
20150081753 | TECHNIQUE FOR PERFORMING ARBITRARY WIDTH INTEGER ARITHMETIC OPERATIONS USING FIXED WIDTH ELEMENTS - One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units. | 03-19-2015 |
20150095394 | MATH PROCESSING BY DETECTION OF ELEMENTARY VALUED OPERANDS - One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time. | 04-02-2015 |
20150113254 | EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE - A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction. | 04-23-2015 |
20150193203 | EFFICIENCY IN A FUSED FLOATING-POINT MULTIPLY-ADD UNIT - A four cycle fused floating point multiply-add unit includes a radix 8 Booth encoder multiplier that is partitioned over two stages with the compression element allocated to the second stage. The unit further includes an improved shifter design. Processing logic analyzes the input operands, detects values of zero and one, and inhibits portions of the processing logic accordingly. When one of the multiplicand inputs has a value of zero or one, the required multiplication becomes trivial, and the unit inhibits the associated coding logic and data transfer to reduce power consumption. The unit then performs an add-only operation. When the addend input has a value of zero, the addition becomes trivial, and the unit inhibits the improved shifter and data transfer to further reduce power consumption. The unit then performs a multiply-only operation. | 07-09-2015 |
Patent application number | Description | Published |
20120079160 | METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITIONS ON A PLATFORM - A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention. | 03-29-2012 |
20130007491 | ENHANCED INTERCONNECT LINK WIDTH MODULATION FOR POWER SAVINGS - Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed. | 01-03-2013 |
20130007502 | REPURPOSING DATA LANE AS CLOCK LANE BY MIGRATING TO REDUCED SPEED LINK OPERATION - Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed. | 01-03-2013 |
20130279622 | METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF HIGH SPEED COMMUNICATION LINKS - A method and system to reduce the power supply noise of a platform during the training of high speed communication links. In one embodiment of the invention, the device has logic to stagger a bit lock pattern for each of one or more communication links and scramble a training sequence for each of the one or more communication links. By doing so, it removes the need for anti-noise circuits and in turn, reduces the silicon area and power of the devices. Further, by having the logic in the physical layers to facilitate the training of the communication links, it eliminates the need to redesign the package of the devices to shift the resonant frequencies. | 10-24-2013 |
20140002102 | ELECTRICAL MARGINING OF MULTI-PARAMETER HIGH-SPEED INTERCONNECT LINKS WITH MULTI-SAMPLE PROBING | 01-02-2014 |
20140006677 | EMBEDDED CONTROL CHANNEL FOR HIGH SPEED SERIAL INTERCONNECT | 01-02-2014 |
20140095751 | FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE - Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed. | 04-03-2014 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140114887 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks. | 04-24-2014 |
20140115207 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 04-24-2014 |
20140115374 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence. | 04-24-2014 |
20140215112 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a predefined sequence on each of the lanes. | 07-31-2014 |
20150067207 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics. | 03-05-2015 |
20150067208 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 03-05-2015 |
20150067210 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks. | 03-05-2015 |
20150205741 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks. | 07-23-2015 |