Patent application number | Description | Published |
20080199799 | Electrostatic image developer, process cartridge, and image forming apparatus - An electrostatic image developer contains a toner and a carrier having a resin coating layer formed on the surface of a core material containing a ferrite component, wherein a ratio R1/R2 is from 0.88 to 0.92 where R1 is the resistance value (Ω) of the developer having a toner concentration of 2 mass % in a state formed into a magnetic brush, at an applied voltage of 10 | 08-21-2008 |
20090061333 | CARRIER FOR ELECTROSTATIC LATENT IMAGE DEVELOPMENT, AND DEVELOPER FOR ELECTROSTATIC LATENT IMAGE DEVELOPMENT, METHOD OF FORMING AN IMAGE, DEVELOPER CARTRIDGE FOR ELECTROSTATIC LATENT IMAGE DEVELOPMENT, PROCESS CARTRIDGE AND IMAGE FORMING APPARATUS USING THE SAME - A carrier for developing an electrostatic latent image includes carrier particles, and the carrier particles include magnetic particles and a coating layer coating the surfaces of the magnetic particles. The BET specific surface area of the magnetic particles is 0.1300 m | 03-05-2009 |
20090109448 | ELECTROSTATIC CHARGE IMAGE DEVELOPING CARRIER, ELECTROSTATIC CHARGE IMAGE DEVELOPER, ELECTROSTATIC CHARGE IMAGE DEVELOPER CARTRIDGE, PROCESS CARTRIDGE, IMAGE FORMING METHOD AND IMAGE FORMING APPARATUS - An electrostatic charge image developing carrier includes: a magnetic particle; and a resin coating layer that covers a surface of the magnetic particle with a resin, the resin coating layer containing an acid having a cyclic diterpene structure and either of carbon black or nigrosine dispersed therein. | 04-30-2009 |
20090111042 | ELECTROSTATIC CHARGE IMAGE DEVELOPER, PROCESS CARTRIDGE AND IMAGE FORMING APPARATUS - An electrostatic charge image developer includes a toner containing an external additive and a carrier comprising a resin-coated layer formed on a surface of a core material. The average shape factor SF1 of the toner is from 125 to 135, the number of particles having shape factor SF1 of less than 125 is from 5% to 30% by number with respect to the total number of toner particles, the number of particles having shape factor SF1 of greater than 135 is from 5% to 30% by number with respect to the total number of toner particles, the scratch line width in a scratch strength test of the resin used in the resin-coated layer is from 80 μm to 200 μm, and the scratch depth is from 60 μm to 150 μm. | 04-30-2009 |
20100330492 | CARRIER FOR ELECTROSTATIC DEVELOPMENT, DEVELOPER FOR ELECTROSTATIC DEVELOPMENT, DEVELOPER CARTRIDGE FOR ELECTROSTATIC DEVELOPMENT, PROCESS CARTRIDGE AND IMAGE FORMING APPARATUS - The invention provides a carrier for electrostatic development, including ferrite particles and a coating layer including a resin having a cycloalkyl group, the ferrite particles including strontium in an amount of from about 0.1% by weight to about 1.0% by weight and having a BET specific surface area of from about 0.13 m | 12-30-2010 |
20110020747 | ELECTROPHOTOGRAPHIC CARRIER, ELECTROPHOTOGRAPHIC DEVELOPER, PROCESS CARTRIDGE AND IMAGE FORMING DEVICE - An electrophotographic carrier includes a magnetic core material and a resin layer that coats the magnetic core material, the resin layer comprising a resistance control agent and a polymer including a repeating unit derived from an alicyclic group-containing methacrylic ester, the resin layer including a monomer as a base material of the repeating unit in the polymer in an amount of from about 0.5% by weight to about 3.0% by weight relative to the total amount of the resin layer. | 01-27-2011 |
20110045399 | ELECTROSTATIC IMAGE DEVELOPING CARRIER, ELECTROSTATIC IMAGE DEVELOPER, PROCESS CARTRIDGE, IMAGE FORMING METHOD AND IMAGE FORMING APPARATUS - An electrostatic image developing carrier includes a ferrite particle and a resin layer that coats the ferrite particle, wherein a magnesium element content of the ferrite particle is from about 3.0% by weight to about 20.0% by weight; wherein a manganese element content of the ferrite particle is from about 0.2% by weight to about 0.8% by weight; and wherein a content of toluene is more than about 100 ppm and not more than about 2,000 ppm. | 02-24-2011 |
20110236814 | CARRIER FOR DEVELOPING ELECTROSTATIC CHARGE IMAGE, DEVELOPER FOR ELECTROSTATIC CHARGE IMAGE, PROCESS CARTRIDGE AND IMAGE FORMING APPARATUS - A carrier for developing an electrostatic charge image, including a core, and a coating layer including a resin and inorganic oxide particles that exhibit electroconductivity, by which the core is coated, wherein the inorganic oxide particles have, when they are aggregated, an aggregation size of or when they are not aggregated, a primary particle size of, from 230 nm to 970 nm. | 09-29-2011 |
20140064803 | FIXING DEVICE AND IMAGE FORMING APPARATUS - A fixing device includes a fixing rotary body that heats and pressurizes, together with a recording medium, toner having particle diameter of 4.5 [μm] or less and a softening point of 100 [° C.] or higher and 125 [° C.] or lower to fix the toner on the recording medium, a heating unit that heats the fixing rotary body, and a pressurizing unit that sandwiches and pressurizes the toner and the recording medium in a contact part formed by the fixing rotary body, wherein the maximum pressure in the contact part is equal to or more than 2.9×10 | 03-06-2014 |
20140178100 | ELECTROSTATIC IMAGE DEVELOPER AND IMAGE FORMING APPARATUS - An electrostatic image developer includes a toner containing an external additive having a volume-average particle size of about 80 to 400 nm and an average circularity of about 0.7 to 0.85. The developer is used in an image forming apparatus including an image-carrying member having a top surface layer containing fluorocarbon resin particles, and a developer-carrying member that faces the image-carrying member and carries an electrostatic image developer, in which a value obtained by dividing the amount of developer on the developer-carrying member [g/m | 06-26-2014 |
20150268570 | BRILLIANT TONER, ELECTROSTATIC CHARGE IMAGE DEVELOPER, TONER CARTRIDGE, AND PROCESS CARTRIDGE - A brilliant toner includes flake shape toner particles containing a binder resin and a flake shape metallic pigment. The brilliant toner further includes tabular particles containing a Ti element. | 09-24-2015 |
Patent application number | Description | Published |
20110041975 | TIRE TUBE - An object of the invention is to provide a tire tube which has excellent air impermeability and such excellent durability that the occurrence of cracks in the tube main body is prevented in a contact surface between the tube main body and an inner circumferential surface of the tire. The tire tube of the invention includes a tube main body having a multilayer structure in which at least one rubber layer and at least one thermoplastic resin layer made of a thermoplastic resin or a thermoplastic elastomer composition obtained by blending an elastomer in a thermoplastic resin are laminated together. In at least a region where the tube main body is in contact with the inner circumferential surface of the tire tread part, the rubber layer is placed as the outermost layer of the multilayer structure, and the thermoplastic resin layer is placed inside the outermost layer. | 02-24-2011 |
20120063557 | Phase adjustment circuit, receiving apparatus and communication system - A phase adjustment circuit includes: a serial-to-parallel conversion section configured to convert serial data including a synchronization pattern inserted into a predetermined position into parallel data in response to a clock; a synchronization-pattern-position detection section configured to detect the position of the synchronization pattern in the parallel data generated by the serial-to-parallel conversion section; and an adjustment section configured to adjust the phases of the parallel data and the clock to conform to a position detected by the synchronization-pattern-position detection section as the position of the synchronization pattern in accordance with information on the position of the synchronization pattern. | 03-15-2012 |
20140055473 | IMAGE DATA PROCESSING CIRCUIT AND DISPLAY SYSTEM - There is an image data processing circuit including a memory storing input image data, the input image data being limited to a specific number of colors or to a specific image range, and a correction processing part replacing, when a predetermined tone change is present between a pixel in image data previous by one frame whose data is stored by the memory and a pixel in image data in a current frame whose data is input, a relevant pixel in the current frame with a color of a specific tone. The memory is built in an integrated circuit included in the correction processing part. | 02-27-2014 |
20140369406 | IMAGE COMPRESSION CIRCUIT, IMAGE COMPRESSION METHOD, AND TRANSMISSION SYSTEM - An image compression circuit includes: a transform section configured to transform a plurality of pieces of pixel data into a plurality of pieces of coefficient data; and a quantization section configured to obtain a quantization parameter based on a predetermined number of pieces of the coefficient data, and to quantize the predetermined number of pieces of the coefficient data with use of the quantization parameter. | 12-18-2014 |
Patent application number | Description | Published |
20080222204 | Data Processing Apparatus, Data Processing Method, and Computer Program - A data processing apparatus includes an input section configured to receive data to be encoded, a first pseudo-random-number generating section configured to generate a first pseudo-random number, a second pseudo-random-number generating section configured to a second pseudo-random number, an address determining section configured to determine matrix address candidate values on the basis of a bit string of the second pseudo-random number generated by the second pseudo-random-number generating section, a matrix generating section configured to generate a matrix in which pixel values based on constituent bit values of the first pseudo-random number generated by the first pseudo-random-number generating section are set at matrix positions designated on the basis of the matrix address candidate values, and an encoding section configured to generate encoded data by executing exclusive OR operations between corresponding positional data in the matrix generated by the matrix generating section and the received data. | 09-11-2008 |
20080232713 | Image Matching Method, Image Matching Apparatus, and Program - To provide an image matching method, an image matching apparatus, and a program able to perform a matching images at a high accuracy. A Hough transform unit | 09-25-2008 |
20090169116 | COMPARISON METHOD, COMPARISON SYSTEM, COMPUTER, AND PROGRAM - A comparison apparatus | 07-02-2009 |
20100040265 | REGISTRATION DEVICE, VERIFICATION DEVICE, AUTHENTICATION METHOD AND AUTHENTICATION PROGRAM - A registration device, verification device, authentication method and authentication program that can improve the accuracy of authentication are proposed. A predetermined process is performed for an image signal obtained as a result of taking a picture of a image-capturing target which is given as an object for biometrics authentication and which is a predetermined part of a living body; a characteristic part of the image-capturing target is extracted from the image signal; the Hough transform is carried out by characteristic extraction means for the extracted characteristic part; a plurality of characteristic parameter points are extracted from a parameter point obtained as a result of the Hough transform under a predetermined extraction condition; and a determination is made as to whether the plurality of characteristic parameter points are those to be registered or to be compared with the registered one according to an angle component of the plurality of the characteristic parameter points. | 02-18-2010 |
20100158342 | Image matching method, program, and image matching system - An image matching method capable of matching images with a high precision and a program and an image matching system for the same, providing a conversion unit for performing image processing based on a registered image and a match image for converting points in each image to patterns of curves based on a distance from a reference position to the closest point on a straight line passing through each point in the image from the reference position and an angle formed by a straight line passing through the reference position and the closest point and an x-axis as a reference axis including the reference position, converting linear components in the images to patterns of a plurality of overlapped curves, and generating converted images, a correlation value generation unit for performing correlation processing based on the converted images and generating a correlation value, and a matching unit for performing the matching based on a signal indicating the correlation value generated by the correlation value generation unit. | 06-24-2010 |
Patent application number | Description | Published |
20080217553 | FOCUSING METHOD OF CHARGED PARTICLE BEAM AND ASTIGMATISM ADJUSTING METHOD OF CHARGED PARTICLE - A focusing method of a charged particle beam includes measuring a first set value to focus a beam on a position of a reference plane by using a lens coil, acquiring a first factor to change a set value of an electrostatic lens depending on a distance and a second factor to change a set value of the coil depending on a distance, measuring a level distribution of a target plane, correcting the first set value by using the second factor to correct a focal point position of the beam in the coil from the position of the reference plane to an intermediate level position of the level distribution of the target plane, and correcting a second set value of the lens depending on a level position of the target plane by using the first factor to correct a focal point position of the beam by the lens. | 09-11-2008 |
20090314950 | LITHOGRAPHY APPARATUS AND FOCUSING METHOD FOR CHARGED PARTICLE BEAM - A lithography apparatus includes a unit irradiating a charged particle beam; first and second aperture plate members configured to shape the beam; first and second coils configured to be arranged between the unit and the first aperture plate member, to temporarily deflect the beam, to change a direction of the beam after the temporarily deflecting, and to deflect the beam to a position where the beam passes through the first aperture plate member by the changing; a lens configured to be arranged between the first and second aperture plate members and to control a focal position of the beam having passed through the first aperture plate member; and a unit configured to calculate a difference between positions of the beam on the second aperture plate member obtained by different sets of amounts of deflection at a same focal position when a combination of one of focal positions of the beam controlled by the lens and one of sets of amounts of deflection of the beam obtained by the first and second coils is changed. | 12-24-2009 |
20100001203 | METHOD OF ACQUIRING OFFSET DEFLECTION AMOUNT FOR SHAPED BEAM AND LITHOGRAPHY APPARATUS - A method of acquiring an offset deflection amount for a shaped beam, includes forming reference images of first and second figures which can be shaped by first and second aperture plates placed on a lithography apparatus; forming, using design data of a mark, a reference image of the mark; forming a first convolution reference image obtained by a convolution calculation of the reference image of the mark and the reference image of the first figure and a second convolution reference image obtained by a convolution calculation of the reference image of the mark and the reference image of the second figure; respectively scanning over the mark with charged particle beams having shaped into the first and second figures by using the first and second aperture plates to acquire optical images of the first and second figures; forming a first convolution synthesis image obtained by a convolution calculation of the first convolution reference image and the optical image of the first figure and a second convolution synthesis image obtained by a convolution calculation of the second convolution reference image and the optical image of the second figure; calculating center-of-gravity positions of the first and second convolution synthesis images; and calculating an offset deflection amount for the charged particle beam having shaped into the second figure to match reference positions of the first and second figures based on the center-of-gravity positions of the first and second convolution synthesis images to output a result calculated. | 01-07-2010 |
20130177855 | CHARGED-PARTICLE BEAM DRAWING METHOD, COMPUTER-READABLE RECORDING MEDIA, AND CHARGED-PARTICLE BEAM DRAWING APPARATUS - A charged-particle beam drawing method includes: storing a plurality of time interval patterns defining time intervals for performing a diagnosis of a drift amount of charged-particle beam; drawing a predetermined drawing pattern on a sample by irradiating the beam on the sample; receiving first event information including occurrence of event and type of event; acquiring region information specifying a region being drawn by the beam; selecting a specific time interval pattern from the plurality of time interval patterns based on the type of the event of the first event information and the region information; diagnosing the drift amount of the beam based on the specific time interval pattern, until second event information is received, the second event information includes occurrence of event and type of event; and drawing a predetermined drawing pattern on the sample while performing a drift correction of the charged-particle beam, based on the diagnosing. | 07-11-2013 |
20140166869 | CHARGED PARTICLE BEAM WRITING METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND CHARGED PARTICLE BEAM WRITING APPARATUS - A charged particle beam writing method according to embodiments of the present disclosure includes: storing in a charged particle beam writing apparatus a position coordinate at which a drift amount is diagnosed; storing in the charged particle beam writing apparatus first and second time interval patterns which define time intervals to diagnose the drift amount of the charged particle beam; performing first writing of irradiating a target object with the charged particle beam, and writing a writing pattern on the target object while diagnosing the drift amount based on the first time interval pattern during the writing; and performing second writing of writing a predetermined writing pattern while diagnosing the drift amount when the writing reaches the position coordinate and diagnosing the drift amount based on the second time interval pattern during the writing after the writing reaches the position coordinate. | 06-19-2014 |
Patent application number | Description | Published |
20110007194 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - A solid-state imaging device and an electronic device that includes the solid-state imaging device prevents shifting of a photoelectric conversion region due to long-wavelength light passing to subsurface portions of the solid-state imagine device. The device include a photo diode having an upper layer of a first conductivity type formed over a second layer having an accumulation region of a second conductivity type. The upper layer is a light-receiving portion of the photodiode. A multi-stage element isolation layer is included and has a plurality of layers of the first conductivity type, such that a first lateral side of a first stage of the multi-stage layer abuts the accumulation portion, and a second stage of the multi-stage layer is separated by a width W from the accumulation region of an intermediate portion of a second conductivity type. | 01-13-2011 |
20120057042 | Solid-state image pickup device and signal processing method therefor - Solid-state image pickup device and processing method, with A/D conversion on pixel signals read from a pixel array part that effectively achieves reductions in power consumption, size and price while retaining a high-quality image output. The device includes a pixel array part, a CDS (correlated double sampling) circuit, and an A/D converter. A pixel signal read via a signal line is subjected to noise elimination processing in the CDS circuit, and is then inputted into the A/D converter. The A/D converter includes a ΔΣ modulator and a digital filter to perform highly accurate A/D conversion. The A/D converter can also be provided at the front stage of the CDS circuit. | 03-08-2012 |
20130161486 | IMAGING DEVICE - An imaging device includes: a plurality of first pixels, each including a photodiode and in-pixel transistors and having a light-blocking metal film blocking part of light entering the respective first pixels; and a plurality of second pixels, each including a photodiode and in-pixel transistors and having no light-blocking metal film; and each of the photodiodes included in the first pixels or the second pixels is surrounded with a metal frame. | 06-27-2013 |
20140043514 | SOLID-STATE IMAGE PICKUP DEVICE AND SIGNAL PROCESSING METHOD THEREFOR - The device includes an pixel array part having a plurality of unit pixels, a CDS (correlated double sampling) circuit, and an A/D converter. A pixel signal read from a pixel array part via a signal line is subjected to CDS processing (noise elimination processing) in the CDS circuit, and then this pixel signal is inputted into the A/D converter which performs A/D conversion on the pixel signal. The A/D converter includes a ΔΣ modulator and a digital filter to perform highly accurate A/D conversion. The invention can also be applied to a construction in which an A/D converter is provided at the front stage of the CDS circuit. | 02-13-2014 |
Patent application number | Description | Published |
20100327366 | SEMICONDUCTOR DEVICE - A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor. | 12-30-2010 |
20120028455 | Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained. | 02-02-2012 |
20140327064 | METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD) - In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO | 11-06-2014 |
Patent application number | Description | Published |
20100188116 | IMPEDANCE ADJUSTING CIRCUIT - An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal. | 07-29-2010 |
20110057720 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 03-10-2011 |
20110057721 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 03-10-2011 |
20110057722 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data. | 03-10-2011 |
20110255354 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data. | 10-20-2011 |
20120026812 | MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 02-02-2012 |
20120200364 | OSCILLATOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal. | 08-09-2012 |
20120223769 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 09-06-2012 |
20130343144 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 12-26-2013 |
20140016401 | MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 01-16-2014 |
20140119142 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data. | 05-01-2014 |
20140203882 | OSCILLATOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal. | 07-24-2014 |
20150055398 | SEMICONDUCTOR INTEGRATE CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data. | 02-26-2015 |
Patent application number | Description | Published |
20110154138 | FAILURE ANALYSIS METHOD, FAILURE ANALYSIS APPARATUS, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, electrical test results of a semiconductor memory arrayed in a logical address order are stored in a first memory secured in a main memory, a plurality of second memory areas in each of which loading and storing of each data in a unit size is performed is secured in the main memory, FBMs in which pass/fail information is arrayed in a physical address order are generated based on different parts of the electrical test results stored in the first memory area, respectively, the FBMs generated from the different parts of the electrical test results are stored in the second memory areas, respectively, and the FBMs stored in the second memory areas, respectively, are output. | 06-23-2011 |
20140043360 | SEMICONDUCTOR DEVICE FAILURE ANALYSIS SYSTEM AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image. | 02-13-2014 |