Hyunsu
Hyunsu Bae, Seoul KR
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20150233984 | ENERGY MEASURING APPARATUS AND ENERGY MEASUREMENT INFORMATION LABELING SYSTEM USING SAME - An energy measuring apparatus includes: a power information collecting unit for collecting the power information including the power signal at least one penetration point of power for the multiple facility equipments; an operating state extracting unit for extracting the operating state or the changing pattern of the operating state of facility equipments by classifying the normal state and the transitional state of the power change from the collected power information; and a data set generating unit for generating data sets for the individual facility equipment matching with operating state or the changing pattern of operating state through the signal correlations according to the power consumption characteristic of individual facility equipments. | 08-20-2015 |
20150377934 | Energy Measuring Unit Compatible with Circuit Breaker in Distribution Board - Embodiments herein provide an energy measuring unit, compatible with a circuit breaker in a distribution board, for measuring energy usage information. The energy measuring unit includes a voltage input terminal, and a voltage measuring unit electrically, connected to the voltage input terminal, configured to measure a voltage value. The energy measuring unit measures energy usage information using the voltage value. Further, the energy measuring unit includes a communication unit configured to communicate the energy usage information to a remote electronic device. In an embodiment, the voltage input terminal is configured to fix the energy measuring unit to the distribution board to receive voltage from a busbar of the distribution board. The energy measuring unit is configured to be compatible with a branch circuit breaker coupled with the busbar of the distribution board. | 12-31-2015 |
Hyunsu Cha, Seoul KR
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20150333844 | METHOD FOR TRANSMITTING AND RECEIVING DATA ON THE BASIS OF ADAPTIVE BLIND INTERFERENCE ALIGNMENT - The present invention provides adaptive blind interference alignment (BIA) methods capable of controlling interference between users without channel information, and devices for supporting the same. A method for transmitting a signal according to the adaptive BIA method in a wireless access system, as one embodiment of the present invention comprises the steps of enabling a transmitter to constitute a first block including preferred signals and interference signals on the basis of the number of receivers within a cell and the number of reception modes of the receiver; enabling the transmitter to constitute a second block including one kind of signal from the preferred signals or the interference signals; enabling the transmitter to constitute alignment blocks for each receiver by combining the first block with the second block; and enabling the transmitter to transmit the alignment blocks to the receivers according to transmission symbol patterns corresponding to the alignment blocks. | 11-19-2015 |
Hyunsu Cho, Daejeon KR
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20100097416 | ORGANIC DRY JET PRINTING HEAD, AND PRINTING DEVICE AND METHOD USING THE SAME - Disclosed herein is an organic dry jet printing head and a printing device and method using the same, in which a pattern (thin film) can be formed through the repetitive injection of a high-speed jet by regularly and repeatedly opening and closing an on-off valve in a pattern (thin film) forming region using the on-off valve and a control unit. The organic dry jet printing head and the printing device and method using the same are advantageous in that processes can be performed at atmospheric pressure, a large-area organic electronic device can be manufactured and high-resolution patterns can be printed, thereby improving productivity and economic efficiency. | 04-22-2010 |
Hyunsu Choi, Suwon-Si KR
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20100214816 | SEMICONDUCTOR DEVICES SUPPORTING MULTIPLE FUSE PROGRAMMING MODES - Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift register includes a first shift register configured to generate first select signals and a second shift register configured to generate second select signals corresponding to data to be programmed to the plurality of fuses. Respective ones of the program circuits may be configured to program respective ones of the fuses responsive to respective pairs of the first select signals and the second select signals. | 08-26-2010 |
20100238755 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER SAVING MODE - A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode. | 09-23-2010 |
20140313819 | SYSTEM ON CHIP INCLUDING DUAL POWER RAIL AND VOLTAGE SUPPLY METHOD THEREOF - A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell. | 10-23-2014 |
Hyunsu Hong, Gyeonggi-Do KR
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20150040211 | MOTION INPUT DEVICE FOR PORTABLE TERMINAL AND OPERATION METHOD USING THE SAME - The present invention relates to a motion input device for portable terminal and an operation method using the same. A motion input device of a portable terminal of the present invention includes a sensor unit configured to collect a sensor signal from at least one sensor; an operation recognition unit configured to generate a motion signal corresponding to an operation of portable terminal based on the sensor signal; a scenario preparation unit configured to generate an input scenario based on at least one motion signal; and a scenario mapping unit configured to detect, in a scenario database, a standards scenario corresponding to the input scenario, and to generate an input signal corresponding to the standards scenario. | 02-05-2015 |
Hyunsu Jang, Gyeonggi-Do KR
Hyunsu Jun, Seongnam-Si KR
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20150325611 | SEMICONDUCTOR PACKAGES INCLUDING ELECTRICAL INSULATION FEATURES - A semiconductor package can include a substrate and a semiconductor chip inside the semiconductor package mounted on the substrate. A first conductive pattern can be on the substrate inside the semiconductor package and can be electrically connected to an input/output of the semiconductor chip. A holder can be on the substrate, where the holder can be configured to provide a recess in which the semiconductor chip is located. An electrically insulating adhesive layer can be configured to electrically insulate the first conductive pattern from an Electric Static Discharge (ESD) source located outside the semiconductor package and configured to adhere the holder to the substrate. | 11-12-2015 |
20160005778 | Semiconductor Package and Method for Manufacturing the Same - Provided is a semiconductor package including: a substrate; an image sensor chip disposed on the substrate and including a first surface that faces the substrate and a second surface that is opposed to the first surface; an adhesion layer interposed between the substrate and the image sensor chip; and a first cavity surrounded by the first surface, an upper surface of the substrate and a side surface of the adhesion layer. The first surface includes a first central portion and a first edge portion, the adhesion layer includes a first adhesion part directly contacting the first central portion and a second adhesion part directly contacting the substrate, and the first adhesion part has an area corresponding to about 5% to about 50% of an area of the first surface. | 01-07-2016 |
Hyunsu Kim, Bucheon-Si KR
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20150103783 | COMMUNICATION METHOD FOR PREVENTING SIGNAL COLLISION IN PEER AWARE COMMUNICATION SYSTEM AND APPARATUS FOR TRANSMITTING/RECEIVING USING THE METHOD - A communication method in a peer aware communication system and an apparatus for transmitting/receiving using the communication method are provided. A block signal for informing of channel occupation is generated and then is transmitted through an interval in which a message signal including a preamble signal is not transmitted. A subcarrier for the block signal is different from a subcarrier for the preamble signal. | 04-16-2015 |
Hyunsu Kim, Suwon-Si KR
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20160064193 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor manufacturing apparatus includes a lower electrode, an upper electrode, first and second high-frequency power sources, and a controller. The lower electrode is disposed in a process chamber, and the upper electrode is disposed over the lower electrode in the process chamber. The first high-frequency power source is connected to one of the lower electrode and the upper electrode, and the second high-frequency power source is connected to one of the lower electrode and the upper electrode. The controller is connected to the first and second high-frequency power sources. The first high-frequency power source generates a first high-frequency power used to perform a first capacitively coupled plasma (CCP) process. The second high-frequency power source generates a second high-frequency power used to perform a second CCP process. The controller controls the second high-frequency power source to interrupt the second high-frequency power during the first CCP process. | 03-03-2016 |
Hyunsu Park, Seoul KR
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20140043658 | INPUT APPARATUS AND CONTROL METHOD THEREOF - An input apparatus having a scan function according to the disclosure includes a position detecting unit to acquire position information of each unit image of a scan target object; a unit image acquiring unit to acquire each unit image by using the position information of each unit image; and an object image acquiring unit to acquire an object image of the scan target object by merging the acquired unit images. | 02-13-2014 |
Hyunsu Yoon, Gyeonggi-Do KR
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20140015553 | MEMORY DEVICE AND METHOD FOR MEASURING RESISTANCE OF MEMORY CELL - A memory device includes a plurality of resistive memory units configured to receive a voltage of a corresponding line of a plurality of program/read lines, a plurality of switch units configured to each electrically connect a corresponding one of the resistive memory units with a corresponding line of a plurality of column lines in response to a voltage of a corresponding line of a plurality of row lines, where the program/read lines correspond to the row lines, respectively, a row control circuit configured to turn on the switch units by selecting at least one of the row lines and apply an external voltage to a program/read line corresponding to the selected row line in a first test mode, and a column control circuit configured to select at least one of the column lines and couple the selected column line with a ground voltage terminal in the first test mode. | 01-16-2014 |
20140036569 | RESISTIVE MEMORY DEVICE - A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the first cell array, and a second error correction cell array configured to share column lines of the first error correction cell array. | 02-06-2014 |
20140063894 | E-FUSE ARRAY CIRCUIT AND PROGRAMMING METHOD OF THE SAME - A program method for an e-fuse array circuit includes receiving an address and a multi-bit program data, programming the multi-bit program data in e-fuses designated by the address, reading a multi-bit read data from the e-fuses, and comparing bits of the multi-bit program data with bits of the multi-bit read data, wherein if the bits of the multi-bit program data are identical to the bits of the multi-bit read data, a program operation is terminated; and if the bits of the multi-bit read data are not identical to the bits of the multi-bit program data, then the programming of the multi-bit program data, the reading of the multi-bit read data, and the comparing of the bits are performed again. | 03-06-2014 |
20140068359 | SEMICONDUCTOR DEVICE AND MEMORY DEVICE - A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus. | 03-06-2014 |
20140082438 | ONE-TIME PROGRAM CELL ARRAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability. | 03-20-2014 |
20140126301 | MEMORY DEVICE AND TEST METHOD THEREOF - A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and matching the memory bank address and the row address with each other and programming the matched address to a nonvolatile memory when the data read from the multiple memory banks are different from each other. | 05-08-2014 |
20140126302 | MEMORY DEVICE AND TEST METHOD THEREOF - A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the row address to locations designated by the bank address latched in the latching in a nonvolatile memory when the data read from the multiple memory banks are different from each other. | 05-08-2014 |
20140126304 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips. | 05-08-2014 |
20140126308 | INTEGRATED CIRCUIT AND MEMORY DEVICE - A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed. | 05-08-2014 |
20140126318 | INTEGRATED CIRCUIT INCLUDING E-FUSE ARRAY CIRCUIT - An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage. | 05-08-2014 |
20140126319 | SETTING INFORMATION STORAGE CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME - A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data. | 05-08-2014 |
20150026512 | INTEGRATED CIRCUIT AND MEMORY DEVICE - A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed. | 01-22-2015 |