Patent application number | Description | Published |
20100321617 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - Exemplary embodiments of the present invention disclose a liquid crystal display (LCD) and a method of manufacturing the same. The LCD may have a display area and a peripheral area. An organic layer of the peripheral area may be patterned using a half-tone mask, and a protrusion member may be formed in the peripheral area. Accordingly, the thin film transistor array panel and the corresponding substrate may be prevented from being temporary adhered in the peripheral area such that the density of the liquid crystal molecules filled in the peripheral area may be uniformly maintained and the display quality of the liquid crystal display may be improved. | 12-23-2010 |
20110049519 | Thin Film Transistor Array Panel and Method of Manufacturing the Same - A thin film transistor array panel includes an insulation substrate. A signal line is formed on the insulation substrate. A thin film transistor is connected to the signal line. A color filter is formed on the substrate. An organic insulator is formed on the color filter and includes a first portion and a second portion having different thicknesses. A light blocking member is formed on the second portion of the organic insulator. A difference between the surface height of the first portion of the organic insulator and the surface height of the second portion of the organic insulator is in the range of about 2.0 μm to 3.0 μm. | 03-03-2011 |
20110133193 | THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF - A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape. | 06-09-2011 |
20120135555 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant. | 05-31-2012 |
20120273787 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - In a thin film transistor array panel according to an exemplary embodiment of the present invention, a plasma process using a mixed gas including hydrogen gas and nitrogen gas with a ratio of a predetermined value is undertaken before depositing a passivation layer. In this manner, performance deterioration of the thin film transistor may be prevented and simultaneously, haze in a transparent electrode may be prevented. Alternatively, a first passivation layer is depsoited, then removed. A passivation layer is again re-deposited, such that little or no haze is present in the resulting passivation layer. | 11-01-2012 |
20130234144 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line. | 09-12-2013 |
20140036211 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - Exemplary embodiments of the present invention disclose a liquid crystal display (LCD) and a method of manufacturing the same. The LCD may have a display area and a peripheral area. An organic layer of the peripheral area may be patterned using a half-tone mask, and a protrusion member may be formed in the peripheral area. Accordingly, the thin film transistor array panel and the corresponding substrate may be prevented from being temporary adhered in the peripheral area such that the density of the liquid crystal molecules filled in the peripheral area may be uniformly maintained and the display quality of the liquid crystal display may be improved. | 02-06-2014 |
20150053984 | THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF - A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape. | 02-26-2015 |