Patent application number | Description | Published |
20080265378 | Scribe line layout design - A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing. | 10-30-2008 |
20080280393 | METHODS FOR FORMING PACKAGE STRUCTURES - A method for forming a semiconductor structure includes forming a first connector over at least one pad of a first substrate, the first connector having at least one curved sidewall. An encapsulation layer is formed at least partially over the first connector so as to partially expose a top surface of the first connector. A solder structure is formed, contacting the first connector. | 11-13-2008 |
20080296571 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 12-04-2008 |
20080308932 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 12-18-2008 |
20090008764 | Ultra-Thin Wafer-Level Contact Grid Array - Wafer-level chip-scaled packaging (WLCSP) features are described in a semiconductor die having a plurality of lands providing electrical connection between a surface of the semiconductor die and an active layer of the semiconductor die. Each of the plurality of lands rises above the surface no more than 10 μm. The device also has a plurality of solder bars at corners of the semiconductor die, the plurality of solder bars also rising above the surface no more than 10 μm. The solder bars add overall contiguous surface area to the solder joints between the die package and its final attachment. | 01-08-2009 |
20090014852 | Flip-Chip Packaging with Stud Bumps - A method for forming a package structure is provided. The method includes providing a semiconductor die; providing a package substrate; forming stud bumps on the package substrate; and bonding the semiconductor die to the package substrate, wherein the stud bumps electrically connect the semiconductor die and the package substrate. | 01-15-2009 |
20090096085 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 04-16-2009 |
20100055846 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 03-04-2010 |
20100273296 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 10-28-2010 |
20110006404 | STRUCTURE AND METHOD OF WAFER LEVEL CHIP MOLDED PACKAGING - A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages. | 01-13-2011 |
20110049516 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 03-03-2011 |
20120038020 | SEAL RING STRUCTURE WITH METAL PAD - A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. | 02-16-2012 |
20130082346 | SEAL RING STRUCTURE WITH A METAL PAD - A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. | 04-04-2013 |
20140117568 | STRUCTURE OF WAFER LEVEL CHIP MOLDED PACKAGE - An integrated circuit structure includes a semiconductor chip having a die side and a non-die side, the die side having one or more trenches formed therein. The integrated circuit structure further includes at least one die bonded onto the die side of the semiconductor chip. The integrated circuit structure further includes a protecting material encapsulating the at least one die and substantially filling the one or more trenches. | 05-01-2014 |
20150051860 | AUTOMATIC OPTICAL APPEARANCE INSPECTION BY LINE SCAN APPARATUS - A method of inspecting a structure of a device and a system for doing the same is described. The method includes generating a sample image of a device having a structure to be inspected; identifying a plurality of features of the sample image; comparing the plurality of features to a corresponding plurality of features of a reference image; and locating features in the sample image that deviate from corresponding features of the reference image. The generating step includes moving the device, a detector array or both, relative to one another, wherein the detector array is configured to generate a line of data representing light reflected from the device, and assembling lines of data from the detector array to generate a sample image. | 02-19-2015 |