Patent application number | Description | Published |
20120256298 | MONITORING PATTERN, AND PATTERN STITCH MONITORING METHOD AND WAFER THEREWITH - A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern. | 10-11-2012 |
20120258386 | MODEL OF DEFINING A PHOTORESIST PATTERN COLLAPSE RULE, AND PHOTOMASK LAYOUT, SEMICONDUCTOR SUBSTRATE AND METHOD FOR IMPROVING PHOTORESIST PATTERN COLLAPSE - A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse if d≧5a and c≧1.5b or if 5a>d≧3a and c≧1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided. | 10-11-2012 |
20120259445 | METHOD FOR MATCHING ASSISTANT FEATURE TOOLS - A method for matching assistant feature tools includes the steps of: generating an objective assistant feature according to a specific test layout by a first assistant feature tool; generating a compared assistant feature according to the specific test layout by a second assistant feature tool; and determining whether to accept or reject the second assistant feature tool by comparing the compared assistant feature with the objective assistant feature. | 10-11-2012 |
20120273948 | INTEGRATED CIRCUIT STRUCTURE INCLUDING A COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a barrier layer including a titanium nitride layer and a method for fabricating the same are disclosed. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer connected to the copper layer, wherein the barrier layer comprises a first layer including a tantalum layer and a tantalum nitride layer and a second layer including a titanium nitride layer, the first layer contacts the copper layer and is disposed between the copper layer and the second layer, and the barrier layer has a recess correspondingly above the copper layer; and forming an aluminum (Al) layer disposed in the recess. | 11-01-2012 |
20120273950 | INTEGRATED CIRCUIT STRUCTURE INCLUDING COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer including a CuSiN layer on the copper layer; forming a wetting layer on the barrier layer; and forming an aluminum (Al) layer on the wetting layer. | 11-01-2012 |
20120276730 | METHODS FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20120276731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20120302031 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS FOR PREPARING HIGH-ASPECT-RATIO STRUCTURES - The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (T | 11-29-2012 |
20120302062 | METHOD FOR VIA FORMATION IN A SEMICONDUCTOR DEVICE - A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth. | 11-29-2012 |
20120302065 | PULSE-PLASMA ETCHING METHOD AND PULSE-PLASMA ETCHING APPARATUS - The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (T | 11-29-2012 |
20120302070 | METHOD AND SYSTEM FOR PERFORMING PULSE-ETCHING IN A SEMICONDUCTOR DEVICE - A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl | 11-29-2012 |
20130043529 | Circuit Structure with Vertical Double Gate - A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor. | 02-21-2013 |