Patent application number | Description | Published |
20130181347 | Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. | 07-18-2013 |
20130292831 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 11-07-2013 |
20130332092 | Calibration Kits for RF Passive Devices - A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices. | 12-12-2013 |
20130341800 | Integrated Circuit Packages and Methods for Forming the Same - A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. | 12-26-2013 |
20140027900 | Bump Structure for Yield Improvement - A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components. | 01-30-2014 |
20140045327 | Double Solid Metal Pad with Reduced Area - An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions. | 02-13-2014 |
20140045379 | Package Assembly and Methods for Forming the Same - A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector. | 02-13-2014 |
20140057431 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 02-27-2014 |
20140077356 | Post Passivation Interconnect Structures and Methods for Forming the Same - A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer. | 03-20-2014 |
20140087522 | Reducing Delamination Between an Underfill and a Buffer Layer in a Bond Structure - A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM. | 03-27-2014 |
20140145307 | Seal Ring Structure with Metal-Insulator-Metal Capacitor - A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring. | 05-29-2014 |
20140145346 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region. | 05-29-2014 |
20140151698 | Test Structures for Post-Passivation Interconnect - An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating. | 06-05-2014 |
20140159223 | Apparatus and Method for Package Reinforcement - A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component. | 06-12-2014 |
20140170850 | UBM Structures for Wafer Level Chip Scale Packaging - A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure. | 06-19-2014 |
20140183690 | Guard Ring Design for Maintaining Signal Integrity - A structure includes a metal feature, and a passivation layer having a portion overlapping the metal feature. The passivation layer includes a non-low-k dielectric material. A polymer layer is over the passivation layer. A Post-Passivation Interconnect (PPI) extends into the polymer layer to electrically couple to the metal feature. A guard ring includes a second PPI, wherein the guard ring is electrically grounded. The second PPI substantially encircles the first PPI. | 07-03-2014 |
20140183693 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 07-03-2014 |
20140191394 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 07-10-2014 |
20140203438 | Methods and Apparatus of Packaging of Semiconductor Devices - Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad. | 07-24-2014 |
20140231125 | Interconnect Joint Protective Layer Apparatus and Method - Disclosed herein is a mechanism for forming an interconnect comprising forming a connector on an interconnect disposed on a first surface of a first substrate and applying a nonconductive material in a non-liquid form over the interconnect after forming the connector. The nonconductive material covers at least a lower portion of the interconnect, and at least a portion of the interconnect is exposed. The nonconductive material is formed around the connector by pressing the nonconductive material over the connector with a roller. An angle between a top surface of the nonconductive material and a connector sidewall between about 65 degrees and about 135 degrees. The nonconductive material may be formed to extend under the connector. | 08-21-2014 |
20140231984 | Molding Compound Structure - A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component. | 08-21-2014 |
20140242791 | METHOD OF FORMING BUMP STRUCTURE - A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer. | 08-28-2014 |
20140246772 | Passivation Scheme - An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first passivation layer. A stress buffer layer is disposed over the second passivation layer. A conductive interconnect layer is over and coupled to the conductive pad and over the stress buffer layer with the conductive interconnect layer adjoining sidewalls of the first passivation layer and the stress buffer layer. | 09-04-2014 |
20140246785 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 09-04-2014 |
20140252558 | Methods and Apparatus for Wafer Level Packaging - A semiconductor device comprises a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may comprise a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring. | 09-11-2014 |
20140252593 | Method and Apparatus for Connecting Packages onto Printed Circuit Boards - Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy. | 09-11-2014 |
20140252601 | Interconnect Structures and Methods of Forming Same - Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. | 09-11-2014 |
20140252608 | Method and Apparatus for Packaging Pad Structure - Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing. | 09-11-2014 |
20140252610 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region. | 09-11-2014 |
20140252611 | Ball Amount Process in the Manufacturing of Integrated Circuit - An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness. | 09-11-2014 |
20140256092 | Interconnect Structures and Methods of Forming Same - Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface. | 09-11-2014 |
20140262468 | System and Method for an Improved Interconnect Structure - Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad separated from the trace by a trace gap, which may optionally be at least 10 μm. | 09-18-2014 |
20140264735 | Inductor System and Method - A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed. | 09-18-2014 |
20140264824 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 09-18-2014 |
20140264837 | SEMICONDUCTOR DEVICE WITH POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad. | 09-18-2014 |
20140264846 | Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods - Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater. | 09-18-2014 |
20140264859 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. | 09-18-2014 |
20140264884 | WLCSP Interconnect Apparatus and Method - Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 μm. | 09-18-2014 |
20140264885 | Apparatus and Method for Wafer Separation - A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction. | 09-18-2014 |
20140264927 | Single Mask Package Apparatus and Method - Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land. | 09-18-2014 |
20140266542 | Programmable Inductor - A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects. | 09-18-2014 |
20140367160 | ELECTRIC MAGNETIC SHIELDING STRUCTURE IN PACKAGES - A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line. | 12-18-2014 |
20140374899 | Package with Solder Regions Aligned to Recesses - A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. | 12-25-2014 |
20140374921 | Ball Height Control in Bonding Process - A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component. | 12-25-2014 |
20150017778 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 01-15-2015 |
20150031200 | Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. | 01-29-2015 |
20150048498 | Alignment Structures and Methods of Forming Same - Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface. | 02-19-2015 |
20150069606 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 03-12-2015 |
20150084211 | Package Assembly and Methods for Forming the Same - A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector. | 03-26-2015 |