Patent application number | Description | Published |
20080285808 | INTERPOLATION METHOD FOR IMAGE PICTURES AND IMAGE PROCESSING APPARATUS THEREOF - An interpolation method, applied to image pictures, for interpolating at least one pixel into a position to be interpolated in a target image frame is disclosed. The interpolation method includes receiving a plurality of image fields having a corresponding image object, estimating a motion speed of the image object according to a distance between a first pixel position to which the image object located in a first image field of the plurality of image fields and a second pixel position to which the image object located in a second image field of the plurality of image fields, determining the pixel from the plurality of image fields according to the motion speed of the image object, and interpolating the pixel into the position to be interpolated in the target image frame. | 11-20-2008 |
20080285851 | COLOR CORRECTION METHOD AND APPARATUS OF DISPLAY APPARATUS - The invention discloses a color correction method for adjusting the color performance of a display apparatus. The color correction method first displays a plurality of images on a panel of the display apparatus and measures the chromatic value and the luminance of each image so as to obtain the color characteristics of the display apparatus. According to the color characteristics, a corresponding color matrix is generated which is located at the CIE XYZ color space. Next, an output matrix is outputted by performing an operation between the color matrix and a gain matrix. Next, the elements in gain matrix are adjusted in order to have the output matrix be equal to a target matrix substantially. Finally, the display apparatus is set for calibrating the color performance thereof in accordance with the elements of the adjusted gain matrix. | 11-20-2008 |
20100188570 | VIDEO PROCESSING APPARATUS AND RELATED METHOD FOR DE-INTERLACING - A video processing apparatus for de-interlacing includes a video decoder and a de-interlacing circuit. The video decoder decodes a video data stream to generate an interlaced video signal and transmits a first interlaced control signal. The de-interlacing circuit is coupled to the video decoder, and includes a detecting unit and an interlacing to progressive converting unit. The detecting unit generates a second interlaced control signal according to the interlaced video signal and the first interlaced control signal. The interlacing to progressive converting unit is coupled to the detecting unit for receiving the interlaced video signal as well as the second interlaced control signal and for converting the interlaced video signal into a first progressive video signal according to the second interlaced control signal. | 07-29-2010 |
20130011010 | THREE-DIMENSIONAL IMAGE PROCESSING DEVICE AND THREE DIMENSIONAL IMAGE PROCESSING METHOD - A 3D image processing device comprising: an object detecting unit, for detecting a first location for an object in a first image and a second location for the object in a second image; a disparity determining unit, coupled to the object detecting unit, for computing a disparity result for the object between the first image and the second image according to the first location and the second location; a displacement computing unit, coupled to the disparity determining unit, for computing a first displacement distance of the first image and a second displacement distance of the second image according to the disparity result; and a displacement unit, coupled to the displacement computing unit, for moving the first image and the second image to generate a first displaced image and a second displaced image, according to the first displacement distance and the second displacement distance. | 01-10-2013 |
20150215498 | DEVICE AND METHOD FOR USING AN OVERDRIVE FUNCTION TO DO MOTION SMOOTHING - A device and method using an overdrive function to do smoothing processing of video data including a frame sequence AABB or AABBB is disclosed in the present invention. The device includes a video information generator and an over drive circuit. The video information generator detects a plurality of continuous frames wherein the continuous frames include a current frame and a previous frame. When a second value of the current frame is different from a first value of the previous frame having the same position as that of the second value, the video information generator generates first video information; When the second value of the current frame is the same as the first value of the previous frame having the same position as that of the second value, the video information generator generates second video information. The over drive circuit generates a first target value which is a value between the first value and the second value according to the first video information, and uses the first target value to replace the second value of the current frame; or the overdrive circuit generates a second target value according to the second video information, and uses the second target value to replace the second value of the current frame. | 07-30-2015 |
Patent application number | Description | Published |
20080199783 | Double-Decker Pellicle-Mask Assembly - A pellicle-mask assembly includes a mask substrate having an absorber pattern, and a hard pellicle held against movement with respect to the mask substrate by gas pressure. | 08-21-2008 |
20080233661 | Methods and Systems For Lithography Alignment - Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate. | 09-25-2008 |
20090103068 | EXPOSURE APPARATUS AND METHOD FOR PHOTOLITHOGRAPHY PROCESS - Provided is an exposure apparatus including a variable focusing device. The variable focusing device may include a transparent membrane that may be deformed in the presence of an electric field. The deformation of the transparent membrane may allow the focus length of a radiation beam to be modified. In an embodiment, the variable focusing device may be modulated such that a radiation beam having a first focus length is provided for a first position on an exposure target and a radiation beam having a second focus length is provided for a second position on the exposure target. A method and computer-readable medium are also provided. | 04-23-2009 |
20090258159 | NOVEL TREATMENT FOR MASK SURFACE CHEMICAL REDUCTION - A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask. | 10-15-2009 |
20120082940 | PHOTOLITHOGRAPHY PROCESS FOR SEMICONDUCTOR DEVICE - Provided is a non-transitory computer readable medium including instructions to generate a level sensor map and create a compensation map from the level sensor map. The level sensor map includes a first determination of a first height above a reference plane of a feature disposed on a semiconductor substrate, and a second determination of a second height above the reference plane of a second feature disposed on a semiconductor substrate. The first and second feature are in a single exposure field. The compensation map includes a determination of at least one parameter to be used during exposure of a single field during an exposure process for the semiconductor substrate. | 04-05-2012 |
20120293782 | Methods and Systems for Lithography Alignment - Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate. | 11-22-2012 |
20130137266 | MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES - Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed. | 05-30-2013 |
20130164685 | METHOD AND APPARATUS FOR DRYING A WAFER - The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated. | 06-27-2013 |
20130181320 | Manufacturing Techniques for Workpieces with Varying Topographies - Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed. | 07-18-2013 |
20130188164 | DOUBLE DIPOLE LITHOGRAPHY METHOD FOR SEMICONDUCTOR DEVICE FABRICATION - A method of photolithography including coupling a first aperture to a lithography system, then performing a first illumination process to form a first pattern on a layer of a substrate using the first aperture, thereafter coupling a second aperture to the lithography system, and performing a second illumination process to form a second pattern on the layer of the substrate using the second aperture. The first aperture includes a first pair and a second pair of radiation-transmitting regions. The second aperture includes a second plate having a third pair and a fourth pair of radiation-transmitting regions. | 07-25-2013 |
20130302985 | METHOD OF REMOVING RESIDUE DURING SEMICONDUCTOR DEVICE FABRICATION - A method is described including forming a first photoresist feature and a second photoresist feature on a semiconductor substrate. A chemical material coating is formed on the semiconductor substrate. The chemical material coating interposes the first and second photoresist features. The semiconductor substrate is then rinsed; the rinsing removes the chemical material coating from the semiconductor substrate. The chemical material may mix with a residue disposed on the substrate between the first and second photoresist features. Removing the chemical material coating from the substrate may also remove the residue. | 11-14-2013 |
20140065843 | Method of Forming a Photoresist Layer - A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material. | 03-06-2014 |
20140080067 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate. | 03-20-2014 |
20140111779 | METHOD OF OVERLAY PREDICTION - A method includes receiving a substrate having a material feature embedded in the substrate, wherein receiving the substrate includes receiving a first leveling data and a first overlay data generated when forming the material feature, deposing a resist film on the substrate, and exposing the resist film using a predicted overlay correction data to form a resist pattern overlying the material feature on the substrate, wherein using the predicted overlay correction data includes generating a second leveling data and calculating the predicted overlay correction data using the first leveling data, the first overlay data, and the second leveling data. | 04-24-2014 |
20140151699 | Test Structure Placement on a Semiconductor Wafer - A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. | 06-05-2014 |
20140185025 | System And Method For Lithography Alignment - The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate. | 07-03-2014 |
20140190634 | Method and Apparatus for Drying a Wafer - The present disclosure provides a method of fabricating a semiconductor device. The method includes dispensing a liquid on a wafer. The method includes raising the wafer. The method includes lowering the wafer after the raising. The wafer is spun as it is lowered, thereby removing at least a portion of the liquid from the wafer. The present disclosure also provides an apparatus for fabricating a semiconductor device. The apparatus includes a wafer chuck that is operable to hold a semiconductor wafer and secure the wafer thereto. The wafer has a front surface and a back surface. The apparatus includes a dispenser that is operable to dispense a liquid to the front surface of the wafer. The apparatus includes a mechanical structure that is operable to: spin the wafer chuck in a horizontal direction; and move the wafer chuck downwards in a vertical direction while the wafer chuck is being rotated. | 07-10-2014 |
20140268074 | Lithography System with an Embedded Cleaning Module - The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism. | 09-18-2014 |
20150056724 | INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING - The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask. | 02-26-2015 |
20150064916 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate. | 03-05-2015 |
20150082265 | DESIGN STRUCTURE FOR CHIP EXTENSION - One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields. | 03-19-2015 |
20150118837 | Method Of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings. | 04-30-2015 |
20150128098 | Method and System for Repairing Wafer Defects - A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method may further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between repeating defects. A distance between a first focal point and a second focal point of a lithographic system may be configured to correspond to the spacing between repeating defects. Thus, a first repeating defect and a second repeating defect may be repaired concurrently. | 05-07-2015 |
20150147867 | Method Of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a first cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask. | 05-28-2015 |
20150243500 | METHOD OF FORMING A PHOTORESIST LAYER - A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material. | 08-27-2015 |
20150249039 | Method of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device includes providing a substrate having a first region and a second region, and forming a plurality of mandrel features in the first region with a first spacing. The method further includes forming first spacers along sidewalls of the mandrel features with a targeted width A, and forming second spacers with a first width W | 09-03-2015 |