Patent application number | Description | Published |
20110291232 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-01-2011 |
20110298551 | INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME - A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV. | 12-08-2011 |
20120061795 | Through-Substrate Via Waveguides - A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate. | 03-15-2012 |
20120104575 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 05-03-2012 |
20120119845 | Balun System and Method - A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers. | 05-17-2012 |
20120133446 | Quadrature Voltage Controlled Oscillator Including Transmission Line - A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators. | 05-31-2012 |
20120146680 | DE-EMBEDDING ON-WAFER DEVICES - A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed. | 06-14-2012 |
20120153433 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 06-21-2012 |
20120268229 | Compact Vertical Inductors Extending in Vertical Planes - A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor. | 10-25-2012 |
20120299778 | ANTENNA USING THROUGH-SILICON VIA - An antenna includes a substrate and a top plate disposed over the substrate. At least one feed line is connected to the top plate, and each feed line comprises a first through-silicon via (TSV) structure passing through the substrate. At least one ground line is connected to the top plate, and each ground line comprises a second TSV structure passing through the substrate. The top plate is electrically conductive, and the at least one feed line is arranged to carry a radio frequency signal. The at least one ground line is arranged to be coupled to a ground. | 11-29-2012 |
20130009317 | FORMING GROUNDED THROUGH-SILICON VIAS IN A SEMICONDUCTOR SUBSTRATE - A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate. | 01-10-2013 |
20130032799 | Apparatus and Methods for De-Embedding Through Substrate Vias - A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs. | 02-07-2013 |
20130099352 | STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 04-25-2013 |
20130154053 | INDUCTORS WITH THROUGH VIAS - A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate. | 06-20-2013 |
20130154752 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit. | 06-20-2013 |
20130168809 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 07-04-2013 |
20130200447 | Adjustable Meander Line Resistor - An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor. | 08-08-2013 |
20130200448 | Meander Line Resistor Structure - A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor. | 08-08-2013 |
20130228894 | STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR - The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material. | 09-05-2013 |
20130234305 | 3D TRANSMISSION LINES FOR SEMICONDUCTORS - A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications. | 09-12-2013 |
20130246990 | SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA - A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other. | 09-19-2013 |
20130277794 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 10-24-2013 |
20140008773 | Integrated Antenna Structure - Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure. | 01-09-2014 |
20140041173 | TRANSFORMER WITH BYPASS CAPACITOR - An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors. | 02-13-2014 |
20140070366 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided. | 03-13-2014 |
20140097930 | Structure and Method for a Transformer with Magnetic Features - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 04-10-2014 |
20140117501 | DIFFERENTIAL MOSCAP DEVICE - A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments. | 05-01-2014 |
20140152512 | ANTENNA USING THROUGH-SILICON VIA - An antenna includes a substrate and a conductive top plate over the substrate. A feed line is connected to the top plate, and the feed line comprises a first through-silicon via (TSV) structure passing through the substrate. The feed line is arranged to carry a radio frequency signal. A method of designing an antenna includes selecting a shape of a top plate, determining a size of the top plate based on an intended signal frequency, and determining, based on the shape of the top plate, a location of each TSV of at least one TSV contacting the top plate. A method of implementing an antenna includes forming a first feed line through a substrate, the first feed line comprising a TSV, and forming a top plate over the substrate, the top plate being electrically conductive and connected to the first feed line. | 06-05-2014 |
20140167269 | Methods and Apparatus of Packaging with Interposers - Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. | 06-19-2014 |
20140184460 | ANTENNA STRUCTURES - An antenna formed on a semiconductor structure having a substrate with electrical circuits thereon operationally related to the functionality of an antenna and one or more metallic structures formed by a through silicon via, microbump, copper pillar, or redistribution layer proximate to the substrate. The one or more metallic structures form a radiating element of the antenna. Exemplary antennas thus formed can include a slot antenna, a WLAN slot antenna, a planar invented F antenna (PIFA), a spiral antenna, a dipole antenna, a Yagi antenna, a planar dipole antenna, a vertical dipole antenna, a patch antenna, a helical antenna, a loop patch antenna, and combinations thereof. | 07-03-2014 |
20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 07-24-2014 |
20140211438 | Methods and Apparatus for Transmission Lines in Packages - Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes. | 07-31-2014 |
20140217546 | HELICAL SPIRAL INDUCTOR BETWEEN STACKING DIE - The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies. | 08-07-2014 |
20140252546 | SWITCHED CAPACITOR STRUCTURE - A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units. | 09-11-2014 |
20140252548 | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer - An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer. | 09-11-2014 |
20140253391 | Bond Wire Antenna - An antenna structure includes a substrate having at least one first pad for wire bonding. A chip is mounted on the substrate, and the chip has at least one second pad for wire bonding. At least one bond wire connects the at least one first pad and the at least one second pad. The at least one bond wire is configured to transmit or receive an electromagnetic wave signal in at least one specified frequency for data communication. | 09-11-2014 |
20140258955 | Metal Interconnect Modeling - A method for modeling metal routing includes extracting physical parameters of a metal interconnect for a circuit design, determining a resistance value from a database of metal interconnects with the extracted physical parameters, the resistance value being at a maximum frequency of a frequency range to be simulated, modeling the interconnect with a symmetric lumped transmission line model, and defining a resistance value of the lumped transmission line model to be about 1.05-1.3 times the resistance value taken from the database. | 09-11-2014 |
20140264734 | Inductor With Magnetic Material - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 09-18-2014 |
20140264742 | Integrated Capacitor - A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib. | 09-18-2014 |
20140264745 | Transmission Line Formed Adjacent Seal Ring - An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line. | 09-18-2014 |
20140278197 | 4 Port L-2L De-Embedding Method - Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed. | 09-18-2014 |
20140327005 | Apparatus and Methods for De-Embedding Through Substrate Vias - An apparatus for de-embedding through substrate vias is provided. The apparatus may include pads on a first side of a substrate are coupled to through vias extending through a substrate, wherein pairs of the through vias are interconnected by transmission lines of varying lengths along a second side of the substrate. The apparatus may further include pairs of pads coupled together by transmission lines of the same varying lengths. Apparatuses may include through vias surrounding a through via device under test. The surrounding through vias are connected to the through via device under test by a backside metal layer. The apparatus may further include a dummy structure having an area equal to an area of the backside metal layer. | 11-06-2014 |
20140367831 | VARIABLE CAPACITANCE DEVICES - A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device. | 12-18-2014 |
20140368285 | VOLTAGE-CONTROLLED OSCILLATOR - An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes. | 12-18-2014 |
20140374875 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-25-2014 |
20140375408 | INDUCTOR ASSEMBLY AND METHOD OF USING SAME - An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers. | 12-25-2014 |
20150031184 | METHODS OF MANUFACTURING A PACKAGE - A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line. | 01-29-2015 |
20150048432 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region. | 02-19-2015 |
20150050789 | Meander Line Resistor Structure - A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via. | 02-19-2015 |