Patent application number | Description | Published |
20090091996 | Solid state semiconductor storage device with temperature control function, application system thereof and control element thereof - A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing element is used for sensing the operation temperature of the solid state semiconductor storage device so as to provide a temperature sensing signal to the control unit. According to the temperature sensing signal, the control unit controls the operation mode of the solid state semiconductor storage device for achieving the function of temperature control. | 04-09-2009 |
20100318874 | ELECTRONIC MEMORY DEVICE AND METHOD FOR ERROR CORRECTING THEREOF - An electronic memory device includes a controller and a memory unit. The controller includes a micro processor, a host interface, a memory unit interface connected to the memory unit, a data cache area for provisionally storing data, an ECC unit coupled to the memory unit for testing whether there is any error bit in the data or not, and an error correcting unit coupled to the memory unit. If an error bit in the data is found and can be dealt by the ECC unit, the error bit is then directly recovered by the ECC unit. However, if the error bit exceeds beyond the processing capability of the ECC unit, the error correcting unit is selected to primarily invert predetermined data bit till the number of the error can be successfully recovered by the ECC unit. | 12-16-2010 |
20100332738 | STORAGE DEVICE AND DATA PROCESSING METHOD - A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block. | 12-30-2010 |
Patent application number | Description | Published |
20080199057 | Portable storage device with fingerprint identification function - The present invention discloses a portable storage device with a fingerprint identification function. The portable storage device uses a slim sliding fingerprint identifier to detect a user's fingerprint. The slim sliding fingerprint identifier is installed on a lateral side of a housing of the portable storage device such that after the portable storage device is plugged into the application apparatus, the user can enter an identifying fingerprint through the slim sliding fingerprint identifier for a fingerprint identification. The invention enhances the convenience of the fingerprint identification and reduces the circuit occupying area. | 08-21-2008 |
20090132756 | Portable flash memory storage device that may show its remaining lifetime - A portable flash memory storage device that may show its remaining lifetime according to this invention is provided, in which an average erase count that is stored may be read and, after being processed and converted, is formed into a piece of information on its remaining lifetime that is further shown on a display screen of a display module in the portable flash memory storage device, and an erase is implemented on the portable flash memory storage device for an automatic update of average erase count, allowing a user to decide to replace the device or not depending on a latest remaining lifetime information. | 05-21-2009 |
20090300273 | Flash memory apparatus with automatic interface mode switching - A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency. | 12-03-2009 |
20090307418 | Multi-channel hybrid density memory storage device and control method thereof - The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data. | 12-10-2009 |
20090307537 | Flash storage device with data correction function - A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency. | 12-10-2009 |
20100082883 | Hybrid density memory system and control method thereof - A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table. | 04-01-2010 |
20100095051 | Memory system and a control method thereof - A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table. | 04-15-2010 |
Patent application number | Description | Published |
20080235432 | MEMORY SYSTEM HAVING HYBRID DENSITY MEMORY AND METHODS FOR WEAR-LEVELING MANAGEMENT AND FILE DISTRIBUTION MANAGEMENT THEREOF - The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible. | 09-25-2008 |
20080235433 | HYBRID DENSITY MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF - The present invention discloses a control method for a hybrid density memory storage device. The method arranges physical locations for a file system stored in the storage device. The storage device includes a high density storage space, a low density storage space and a hot list capable of recording a plurality of logical locations. The method includes the following steps: receiving a command; verifying whether the logical location of the command belongs to the logical locations recorded in the hot list; and according to the verification, assigning a physical location of the high density storage space or a physical location of the low density storage space as the physical location corresponding to the logical location of the command. | 09-25-2008 |
20080235468 | HYBRID DENSITY MEMORY STORAGE DEVICE - The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list. | 09-25-2008 |
20100037006 | NON-VOLATILE MEMORY AND CONTROLLING METHOD THEREOF - A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks. | 02-11-2010 |
20110246709 | MEMORY SYSTEM HAVING HYBRID DENSITY MEMORY AND METHODS FOR WEAR-LEVELING MANAGEMENT AND FILE DISTRIBUTION MANAGEMENT THEREOF - The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible. | 10-06-2011 |