Patent application number | Description | Published |
20080212665 | System for monitoring the quality of a communications channel with mirror receivers - A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver. | 09-04-2008 |
20090041060 | Cross Link Multiplexer Bus - A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit. The lengths of the first and the second interconnects are substantially equal. | 02-12-2009 |
20090086753 | METHOD AND SYSTEM FOR EXPLOITING SPARE LINK BANDWIDTH IN A MULTILANE COMMUNICATION CHANNEL - A system for encoding data in a multilane communication channel may include at least one processor operable to generate, from existing control characters in a character set, expanded control characters utilized for controlling the data in each lane of the multilane communication channel. Each lane of the multilane communication channel may transport the data in a similar direction. The at least one processor is also operable to control at least one of the lanes of the multilane communication channel using at least one of the generated control characters. If a first control character of the existing control characters is a start-of-packet control character, the at least one processor is then operable to select a second control character from any other of the generated expanded control characters, and to indicate a start of a packet using the selected second control character for at least one of the lanes. | 04-02-2009 |
20090185565 | SYSTEM AND METHOD FOR USING SEQUENCE ORDERED SETS FOR ENERGY EFFICIENT ETHERNET COMMUNICATION - A system and method for using sequence ordered sets for energy efficient Ethernet communication. Sequence ordered sets can be generated by a first device for communication of parameter(s) to a second device, which parameters can be used in implementing an energy efficient Ethernet control policy. Sequence ordered sets can be used in communication between physical layer devices, or between a physical layer device and a media access control device. In one example, the sequence ordered set can identify a point at which a rate transition is to occur. | 07-23-2009 |
20090187778 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING PERIODS OF LOW LINK UTILIZATION - A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship that enables synchronous switching between them depending on the link utilization state. | 07-23-2009 |
20090204827 | SYSTEM AND METHOD FOR ENERGY SAVINGS ON A PHY/MAC INTERFACE FOR ENERGY EFFICIENT ETHERNET - A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero. | 08-13-2009 |
20090232192 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 09-17-2009 |
20100111100 | SYSTEMS AND METHODS FOR DIGITAL INTERFACE TRANSLATION - Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard. | 05-06-2010 |
20110007785 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 01-13-2011 |
20110066729 | METHOD AND SYSTEM TO PROVIDE BLADE SERVER LOAD BALANCING USING SPARE LINK BANDWIDTH - A method for processing network information in a multi-server platform is disclosed and includes receiving by a blade server manager, capacity utilization information embedded in spare link bandwidth from a plurality of blade servers operably coupled to the blade server manager. Digital information received on a digital communication link may be forwarded to one of the plurality of blade servers. The blade servers may be selected based on the received capacity utilization information. The capacity utilization information may include blade server work load capacity, blade server power saving capacity, blade server CPU percent utilization, and/or data representing blade server interrupt utilization. The blade server manager may be operably coupled to an Ethernet network and/or an external network. | 03-17-2011 |
20110283020 | METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION - Aspects of a method and system for physical layer aggregation are provided. A first portion of one or more circuits of a network device may be operable to implement media access control (MAC) functions, a second portion of the one or more circuits may be operable to perform physical layer aggregation, and a third portion of the one or more circuits may be operable to perform physical layer functions for communicating over a plurality of physical links. The first portion of the one or more circuits may be operable to encapsulate data into a packet comprising a preamble and convey the packet to the second portion of the one or more circuits. The second portion of the one or more circuits may be operable to fragment the packet into a plurality of fragment payloads and convey each of the fragment payloads to the third portion of the one or more circuits, wherein at least one of the plurality of fragment payloads comprises at least a portion of the preamble. The third portion of the one or more circuits may be operable to add a header to the fragment payloads to generate a corresponding plurality of fragments, and send the plurality of fragments over one or more of the plurality of physical links. | 11-17-2011 |
20120124405 | System and Method for Energy Savings on a PHY/MAC Interface for Energy Efficient Ethernet - A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero. | 05-17-2012 |
20120201280 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 08-09-2012 |
20120204045 | System and Method for Reducing Power Consumption During Periods of Low Link Utilization - A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship that enables synchronous switching between them depending on the link utilization state. | 08-09-2012 |
20130077662 | SYSTEMS AND METHODS FOR DIGITAL INTERFACE TRANSLATION - Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard. | 03-28-2013 |