Patent application number | Description | Published |
20090135947 | METHOD OF SELECTING CANDIDATE VECTOR AND METHOD OF DETECTING TRANSMISSION SYMBOL - The present invention relates to a method of detecting a candidate vector and a method of detecting a transmission symbol using the same. According to an embodiment of the present invention, in a multiple input multiple output (MIMO) system using spatial multiplexing (SM), a receiver selects candidate vectors corresponding to a layer located at a last row among a plurality of rearranged layers, and sequentially ranks constellation dots of a next layer for each of the selected candidate vectors. Then, a plurality of arbitrary constellation dots are selected from the ranked constellation dots, accumulated costs of the arbitrary constellation dots are calculated, and a candidate vector is selected in correspondence with a constellation dot having a minimal accumulated cost. Then, a new arbitrary constellation dot is selected in place of the constellation dot selected as the candidate vector, an accumulated cost of the selected arbitrary constellation dot is compared with accumulated costs of the other arbitrary constellation dots, and another candidate vector is selected. | 05-28-2009 |
20090147892 | METHOD AND APPARATUS FOR CANCELING INTERFERENCE - An apparatus for canceling interference includes a plurality of converters, a plurality of interference cancellation units, a plurality of variance detectors, and an output selecting unit. The plurality of converters converts a plurality of received signals to a plurality of frequency domain signals, respectively. The plurality of interference cancellation units cancel interference in the plurality of frequency domain signals using a plurality of interference cancellation schemes to generate a plurality of interference-canceled signals corresponding to the plurality of interference cancellation schemes, respectively. The plurality of variance detectors measure a plurality of amounts of residual interference corresponding to the plurality of interference-canceled signals, respectively. The output selecting unit selects a single interference-canceled signal with the least amount of residual interference from the plurality of interference-canceled signals, based on the plurality of amounts of residual interference. | 06-11-2009 |
20100142654 | METHOD AND APPARATUS FOR SIGNAL DETECTION BASED ON MMSE IN MIMO COMMUNICATION SYSTEM - In a multi-input multi-output communication system receiving signals transmitted through a plurality of transmission antennas by using a plurality of reception antennas, a matrix determining a position of a symbol to be detected from a received signal is calculated at a first symbol detection step, and from the subsequent step, a matrix at the current step is acquired through a simple relationship from the matrix calculated at the previous step to determine a position of a symbol to be detected. | 06-10-2010 |
20100142661 | DEVICE FOR GAIN CONTROL AND METHOD FOR RECEIVING SIGNAL - The present invention relates to a device for gain control and a method for receiving a signal. The device for gain control according to the present invention includes a map interpreter that detects beamforming symbol periods in wireless signals, a power calculator that calculate the average power of the beamforming symbol periods in response to outputs of the map interpreter, a gain calculator that calculates gain control signals on the basis of the output signals of the power calculator, and a switch that outputs gains from the gain control signals, in which the wireless signals are corrected on the basis of the gains. | 06-10-2010 |
20100246548 | BASE STATION, METHOD FOR MANAGING CELL, METHOD FOR DETECTION SIGNAL, TERMINAL AND METHOD FOR TRANSMITTING SIGNAL THEREOF - A base station according to an exemplary embodiment of the present invention includes: a receiver receiving environment information of a first terminal from the first terminal positioned at a cell boundary and receiving usable resource information from a neighbor base station; a resource allocator allocating a resource to the first terminal on the basis of the usable resource information; and a transmitter transmitting information on the resource allocated to the first terminal to the neighbor base station. | 09-30-2010 |
20100272205 | METHOD FOR DETECTING SIGNAL, DEVICE FOR DETECTING SIGNAL, AND RECEIVING DEVICE - The present invention relates to a method for detecting a signal, a device for detecting a signal, and a receiving device. A method for detecting a signal according to the present invention is a method for detecting a signal from a receiving device in a communication system including a multi-output multi-input antenna, including: estimating a channel matrix of a signal received from a plurality of receiving antennas; generating at least one channel matrix groups by aligning the channel matrix and generating at least one transmitting signal group by aligning a transmitting signal to be estimated to correspond thereto; determining a first candidate vector in consideration of all constellation points for a first layer of the at least one transmitting signal group; determining a second candidate vector in consideration of all constellation points for a second layer of the at least one transmitting signal group; generating a final candidate vector including the first candidate vector and the second candidate vector; and calculating a soft output using the final candidate vector. | 10-28-2010 |
20130121248 | WIRELESS BASE STATION AND METHOD OF PROCESSING DATA THEREOF - A clustering wireless base station includes a group digital processor including a plurality of digital units (DU) and a plurality of remote radio frequency units (RRU) that are connected to the group digital processor through a transport network and that are installed in each service target area. In this case, each DU includes a decoder that decodes upward data that is received from the each DU, and each RRU includes an encoder that encodes downward data from the each DU. | 05-16-2013 |
20140003416 | METHOD AND APPARATUS FOR ACQUIRING UPLINK AND DOWNLINK SYNCHRONIZATION BETWEEN A PLURALITY OF BASE STATIONS AND A TERMINAL IN A COOPERATIVE COMMUNICATION NETWORK | 01-02-2014 |
Patent application number | Description | Published |
20100154450 | Air Conditioning System Using Dehumidifying Cooling Device - An air conditioning system using for a dehumidifying cooling device has developed that comprising a heating source for producing hot water, a heat exchanger for transferring heat from the hot water to circulating water, a circulation pump for circulating the resulting hot water heated in the heat exchanger, a heating pipeline connected to the circulation pump for conveying the hot water to a heat supply target area, a user heat exchanger connected to the heating pipeline for conveying hot water to the heat supply target area, a dehumidifying cooling device connected to a hot water pipe of users heat exchanger and installed in each household within the heat supply target area, the dehumidifying cooling device removing moisture from the air by using hot water supplied from the hot water pipe to deal with latent heat load and to lower the temperature of the dehumidified air via evaporation of water contained in the air. | 06-24-2010 |
20100212345 | Dehumidifying Cooling Device for District Heating - A dehumidifying cooling device for district heating is developed that comprising; a case with partitions divided into interior, which are a wet channel consisting of an outside air suction, exhaust and a dry channel for circulated air suction from conditioning area and air supply; a rotating sensible heat exchanger to heat exchange outside air of wet channel with the circulated air in the dry channel; a heating coil between the sensible heat exchanger and the exhaust for raising the temperature of outside air; a dehumidifying wheel for adsorbing and removing moisture contained in the circulated air; the dehumidifying wheel being regenerated by evaporating the adsorbed moisture thereby supplying the evaporated moisture into the high-temperature outside air in the wet channel, and a regenerative-evaporative cooler installed between the circulated air supply and the sensible heat exchanger for cooling the circulated air in the dry channel, the cooled circulated air delivered to the air supply. | 08-26-2010 |
20150027149 | ELECTRIC EXPANSION VALVE CONTROL FOR A REFRIGERATION SYSTEM - A refrigeration system including a condenser having a condenser inlet and a condenser outlet, a compressor fluidly connected to the condenser inlet, and an evaporator including an evaporator inlet and an evaporator outlet. The evaporator outlet is fluidly connected to the compressor. A compressor speed sensor senses an operational speed of the compressor. An electric expansion valve (EEV) is fluidly connected to the condenser outlet and the evaporator inlet. The EEV includes a valve member that is selectively positioned to establish a desired opening to pass refrigerant from the condenser to the evaporator. A controller is electrically connected to the EEV and the compressor speed sensor. The controller establishes the desired opening of the valve member based on one of a cooling mode superheat value and a heating mode super heat value, and the operational speed of the compressor. | 01-29-2015 |
Patent application number | Description | Published |
20090091333 | STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O - The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths. | 04-09-2009 |
20090115473 | LOOP FILTER, PHASE-LOCKED LOOP, AND METHOD OF OPERATING THE LOOP FILTER - A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current. | 05-07-2009 |
20100001379 | Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP - A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network. | 01-07-2010 |
20100020583 | Stacked memory module and system - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 01-28-2010 |
20100177572 | SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device. | 07-15-2010 |
20110248740 | STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O - The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths. | 10-13-2011 |
20110310649 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 12-22-2011 |
20120300528 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 11-29-2012 |
20150088456 | APPARATUS AND METHOD FOR EXTRACTING FEATURE POINT FOR RECOGNIZING OBSTACLE USING LASER SCANNER - An apparatus and method for extracting a feature point to recognize an obstacle using a laser scanner are provided. The apparatus includes a laser scanner that is installed at a front of a traveling vehicle and is configured to obtain laser scanner data having a plurality of layers in real time. In addition, a controller is configured to separate the laser scanner data obtained by the laser scanner into a plurality of layers to extract measurement data present in each layer and determine feature points of the measurement data to classify a type of obstacle based on a plurality of stored feature points. | 03-26-2015 |
20150117122 | SEMICONDUCTOR MEMORY DEVICE CALIBRATING TERMINATION RESISTANCE AND TERMINATION RESISTANCE CALIBRATION METHOD THEREOF - Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node. | 04-30-2015 |
Patent application number | Description | Published |
20110249483 | STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE - A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip. | 10-13-2011 |
20110292708 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 12-01-2011 |
20120086125 | Semiconductor Having Chip Stack, Semiconductor System, and Method of Fabricating the Semiconductor Apparatus - In one embodiment, a semiconductor device includes a plurality of semiconductor chip stacks mounted on a substrate. Bonding terminals disposed on the substrate correspond to the chip stacks, such that at least one chip in each chip stack may be directly connected to a bonding terminal on the substrate and at least one chip in the chip stack is not directly connected to the bonding terminal. The semiconductor chip stacks may each act as one semiconductor device to the outside. | 04-12-2012 |
20120267791 | MULTI CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE MULTI CHIP PACKAGE - A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes. | 10-25-2012 |
20130009278 | STACKED SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION CIRCUITS AND METHOD OF FABRICATING THE STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die. | 01-10-2013 |
20130021866 | Semiconductor Devices Compatible with Mono-Rank and Multi-Ranks - A provided memory device is compatible with a mono-rank or multi-ranks. A plurality of memory layers are stacked in the memory device. The memory device receives an address signal and chip select signals in response to a chip identification signal and a mode signal used to determine a mono-rank or multi-ranks. The plurality of memory layers operate as the mono-rank accessed by the address signal, or operate as the multi-ranks accessed by the chip select signals. | 01-24-2013 |
20130037944 | Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas - A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via. | 02-14-2013 |
20130037964 | SEMICONDUCTOR PACKAGE - A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips. | 02-14-2013 |
20140233292 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 08-21-2014 |
Patent application number | Description | Published |
20120269248 | METHOD AND APPARATUS OF DETECTING SIGNAL BASED ON MINIMUM MEAN SQUARE ERROR IN MULTIPLE INPUT MULTIPLE OUTPUT SYSTEM - A receiver in a multiple-input multiple-output (MIMO) system is provided. The receiver includes a channel estimator estimating a channel based on a receiving signal, a minimum mean square error (MMSE) based reciprocal log likelihood ratio (R-LLR) calculator connected with the channel estimator and calculating an R-LLR based on the receiving signal and the estimated channel, and a channel decoder connected with the MMSE based R-LLR calculator and decoding the channel and the receiving signal based on the calculated R-LLR, wherein the R-LLR is calculated based on the reciprocity. | 10-25-2012 |
20130003897 | METHOD AND APPARATUS FOR DEMODULATING DOWNLINK SIGNAL IN WIRELESS COMMUNICATION SYSTEM - There is provided a method and apparatus in which a user equipment demodulates a downlink signal in a wireless communication system. The user equipment receives a first orthogonal frequency division multiplexing (OFDM) signal from a first node serving the mobile station, receives a second OFDM signal from a second node different from the first node, and demodulates the first OFDM signal and the second OFDM signal in a fast Fourier transform (FFT) section. The first OFDM signal and the second OFDM signal are either normal mode signals each having a first cyclic prefix (CP) or cooperative mode signals each having a second CP, and the second CP has a longer length than the first CP. | 01-03-2013 |
20130034027 | METHOD AND APPARATUS FOR PERFORMING TRANSMISSION AND RECEPTION SIMULTANEOUSLY IN SAME FREQUENCY BAND - There are provided a method and apparatus for transmitting and receiving signals in the same frequency band at the same time. A signal is received using a dual polarization antenna, the main axis of the polarization of the reception signal is predicted by performing adaptive polarization tracking, and polarization filtering is performed in order to remove interference. A signal is transmitted through a polarization completely orthogonal to the tracked polarization. In accordance with the present invention, in a wireless communication system, signals can be transmitted and received in the same frequency band at the same time. | 02-07-2013 |
20130044684 | APPARATUS AND METHOD FOR CONTROLLING COMMUNICATION PATH BETWEEN MULTIPLE DIGITAL UNITS AND MULTIPLE RADIO FREQUENCY UNITS IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to a communication path control apparatus for controlling a communication path between a plurality of DUs and a plurality of RFUs, and a plurality of antennas included in the plurality of RFUs and a wireless communication system including the communication path control apparatus. Each of the plurality of DUs, the plurality of RFUs, and the plurality of antennas has a unique identifier, and the path control apparatus controls paths between the plurality of DUs and the plurality of RFUs based on identifiers. Accordingly, the wireless communication system can transmit and receive a signal through a specific RFU and a specific antenna included in a specific RFU and performs the next-generation wireless BS operation method, such as CoMP and multi-BS MIMO. | 02-21-2013 |