Patent application number | Description | Published |
20090154003 | Systems and Methods for Using an On-the-fly CBD Estimate to Adjust Fly-Height - Various embodiments of the present invention provide systems and methods for using channel bit density estimates to adjust fly-height. For example, various embodiments of the present invention provide methods for adaptively adjusting fly-height. Such methods include providing a storage medium that includes information corresponding to a process data set, and a read/write head assembly that is disposed a variable distance from the storage medium. The process data set is accessed from the storage medium. A first channel bit density estimate is adaptively calculated based at least in part on the process data set and a second channel bit density estimate that was previously calculated. The variable distance is modified based at least in part on the first channel bit density estimate. A third channel bit density is adaptively calculated based at least in part on the process data set and a fourth channel bit density estimate that was previously calculated. The variable distance is modified based at least in part on the third channel bit density estimate. | 06-18-2009 |
20090161245 | Frequency Domain Approach for Efficient Computation of Fixed-point Equalization Targets - Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value. | 06-25-2009 |
20090271670 | Systems and Methods for Media Defect Detection Utilizing Correlated DFIR and LLR Data - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a method for detecting a media defect is disclosed. The method includes deriving a data input from a medium and performing a MAP detection on the data input. The MAP detection provides an NRZ output and an LLR output corresponding to the data input. A product of the NRZ output is correlated with a product of the LLR output to produce a correlated output. The correlated output is compared with a threshold value, and a media defect output is asserted based at least in part on the result of the comparison of the correlated output with the threshold value. | 10-29-2009 |
20090276689 | Using short burst error detector in a queue-based system - A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output. | 11-05-2009 |
20100053787 | Systems and Methods for On-The-Fly Write Pre-compensation Estimation - Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value. | 03-04-2010 |
20100053793 | Systems and Methods for Adaptive Write Pre-Compensation - Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide methods for modifying magnetic information transfer. The methods include retrieving magnetically represented data from a storage medium, and converting the magnetically represented data to a series of data samples. A preceding pattern and a transition status is identified in the series of data samples, and an equalized channel response is computed based on an estimated NLTS value. An error value is computed that corresponds to a difference between the estimated NLTS value and an actual NLTS value, and a pre-compensation value is computed based at least in part on the error value. | 03-04-2010 |
20100070835 | Method and Apparatus for Error Compensation - Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described. | 03-18-2010 |
20100083075 | Methods and Apparatus for Selective Data Retention Decoding in a Hard Disk Drive - Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment. | 04-01-2010 |
20100088357 | Systems and Methods for Memory Efficient Signal and Noise Estimation - Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a N | 04-08-2010 |
20100091629 | Method for detecting short burst errors in LDPC system - The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors. | 04-15-2010 |
20100157458 | Systems and Methods for Dibit Correction - Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal. The dibit correction circuit applies a correction factor calculated based at least in part on the maximum sample, the first side sample and the second side sample to at least a subset of the plurality of samples of the uncorrected dibit signals to yield a plurality of corrected dibit signals. | 06-24-2010 |
20100172046 | Systems and Methods for Equalizer Optimization in a Storage Access Retry - Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails. | 07-08-2010 |
20100177419 | AGC Loop with Weighted Zero Forcing and LMS Error Sources and Methods for Using Such - Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback. | 07-15-2010 |
20100177430 | Systems and Methods for Fly-Height Control Using Servo Address Mark Data - Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium ( | 07-15-2010 |
20100182718 | Systems and Methods for Adaptive CBD Estimation in a Storage Device - Various embodiments of the present invention provide systems and methods for adaptive channel bit density estimation. For example, various embodiments of the present invention provide methods for adaptively estimating channel bit density. Such methods include providing a storage medium ( | 07-22-2010 |
20100185906 | ERROR CORRECTION CAPABILITY ADJUSTMENT OF LDPC CODES FOR STORAGE DEVICE TESTING - Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed. | 07-22-2010 |
20100226033 | Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal. | 09-09-2010 |
20100287420 | Systems and Methods for Adaptive Equalization in Recording Channels - Various embodiments of the present invention provide systems and methods for performing adaptive equalization. For example, various embodiments of the present invention provide methods for adaptive equalization that include providing a data processing system with an equalizer circuit ( | 11-11-2010 |
20100332954 | Systems and Methods for Out of Order Y-Sample Memory Management - Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations. | 12-30-2010 |
20110041028 | Systems and Methods for Retimed Virtual Data Processing - Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples | 02-17-2011 |
20110043938 | Systems and Methods for Fly-Height Control Using Servo Data - Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium. | 02-24-2011 |
20110058631 | Systems and Methods for Enhanced Flaw Scan in a Data Processing Device - Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output. | 03-10-2011 |
20110063747 | Systems and Methods for Timing and Gain Acquisition - Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average. | 03-17-2011 |
20110072335 | BRANCH-METRIC CALIBRATION USING VARYING BANDWIDTH VALUES - In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another. | 03-24-2011 |
20110075718 | Automatic Filter-Reset Mechanism - In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive. | 03-31-2011 |
20110080211 | Systems and Methods for Noise Reduced Data Detection - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output. | 04-07-2011 |
20110093517 | Systems and Methods for Adaptive Target Search - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target. | 04-21-2011 |
20110103527 | Phase Detector For Timing Recovery Loop - In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates. | 05-05-2011 |
20110164669 | Systems and Methods for Determining Noise Components in a Signal Set - Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples. | 07-07-2011 |
20110249361 | FLY-HEIGHT CONTROL USING ASYNCHRONOUS SAMPLING - In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed. | 10-13-2011 |
20110298543 | Systems and Methods for Hybrid Algorithm Gain Adaptation - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern. | 12-08-2011 |
20120026623 | DIBIT EXTRACTION FOR ESTIMATION OF CHANNEL PARAMETERS - In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response. | 02-02-2012 |
20120033316 | Systems and Methods for Format Efficient Calibration for Servo Data Based Harmonics Calculation - Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio. | 02-09-2012 |
20120033323 | Systems and Methods for Servo Data Based Harmonics Calculation - Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a circuit for determining harmonics is disclosed that includes an analog to digital conversion circuit that provides a series of digital samples corresponding to a pattern within a servo data region of a storage medium, and a harmonic calculation circuit. The harmonic calculation circuit is operable to calculate a first harmonic value for the series of digital samples, calculate a second harmonic value for the series of digital samples, and calculate a ratio of the first harmonic value to the second harmonic value. | 02-09-2012 |
20120038998 | Systems and Methods for Phase Offset Based Spectral Aliasing Compensation - Various embodiments of the present invention provide systems and methods for phase offset based spectral aliasing compensation. For example, a circuit for spectral aliasing reduction is disclosed that includes a phase shift circuit operable to phase shift an analog input signal and to provide a phase shifted analog signal; a first analog to digital converter circuit operable to provide a first series of digital samples corresponding to the analog input signal at a sampling frequency; a second analog to digital converter circuit operable to provide a second series of digital samples corresponding to the phase shifted analog signal at the sampling frequency; and an averaging circuit operable to average the first series of digital samples with the second series of digital samples to yield an average output. | 02-16-2012 |
20120056612 | Systems and Methods for Phase Compensated Harmonic Sensing in Fly Height Control - Various embodiments of the present invention provide systems and methods for phase compensated harmonic sensing. For example, a circuit for harmonics calculation is disclosed that includes a phase difference estimation circuit and a phase offset compensation circuit. The harmonic calculation circuit is operable to calculate a first harmonic based on a periodic data pattern and a second harmonic based on the periodic data pattern. The phase difference estimation circuit operable to calculate a phase difference between the first harmonic and the second harmonic. The phase offset compensation circuit operable to align the second harmonic with the first harmonic to yield an aligned harmonic. | 03-08-2012 |
20120068752 | Systems and Methods for Low Latency Noise Cancellation - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period. | 03-22-2012 |
20120068870 | Systems and Methods for Semi-Independent Loop Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output. | 03-22-2012 |
20120069891 | Systems and Methods for Filter Constraint Estimation - Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter. | 03-22-2012 |
20120124454 | Systems and Methods for ADC Sample Based Timing Recovery - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples. | 05-17-2012 |
20120158810 | Systems and Methods for Reducing Filter Sensitivities - Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value. | 06-21-2012 |
20120226958 | METHOD FOR DETECTING SHORT BURST ERRORS IN LDPC SYSTEM - The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gat is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors. | 09-06-2012 |
20120236430 | Systems and Methods for Auto Scaling in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output. | 09-20-2012 |
20120254679 | Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal. | 10-04-2012 |
20120265488 | Systems and Methods for Reliability Assisted Noise Predictive Filtering - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output. | 10-18-2012 |
20120281305 | Systems and Methods for Servo Data Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a codeword detector circuit operable to apply a codeword based data detection algorithm to a data input corresponding to an encoded servo data region to yield a detected output, and a servo address mark processing circuit operable to identify a pre-defined pattern in the detected output. | 11-08-2012 |
20120324307 | Systems and Methods for Retimed Virtual Data Processing - Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. | 12-20-2012 |
20130002462 | Analog to Digital Converter with Generalized Beamformer - Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output. | 01-03-2013 |
20130050005 | Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors - Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors. | 02-28-2013 |
20130097213 | Nyquist Constrained Digital Finite Impulse Response Filter - Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range. | 04-18-2013 |
20130097472 | Systems and Methods for Out of Order Y-Sample Memory Management - Systems and methods for out of order memory management. | 04-18-2013 |
20140233130 | Systems and Methods for Determining Noise Components in a Signal Set - Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples. | 08-21-2014 |