Patent application number | Description | Published |
20110261632 | Combined Write Assist and Retain-Till-Accessed Memory Array Bias - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode. | 10-27-2011 |
20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
20120163109 | MEMORY CIRCUIT AND A TRACKING CIRCUIT THEREOF - Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell. | 06-28-2012 |
20130128680 | READ ASSIST CIRCUIT FOR AN SRAM - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 05-23-2013 |
20140241083 | READ ASSIST CIRCUIT FOR AN SRAM TECHNICAL FIELD - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 08-28-2014 |
20140241089 | READ ASSIST CIRCUIT FOR AN SRAM TECHNICAL FIELD - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 08-28-2014 |
Patent application number | Description | Published |
20130275582 | SYSTEMS AND METHODS FOR TRAP MONITORING IN MULTI-CORE AND CLUSTER SYSTEMS - In a multi-core device or clustered system, instead of snmpd polling for configured monitoring values of an entity to determine if reached a threshold, each core in a multi-core system or node in a clustered system triggers information to the snmpd about entities that may be or are generating SNMP traps. A configured threshold T is distributed among the cores or nodes, as the case may be, based on the number of cores or nodes. If there are ‘n’ cores in a multi-core device, and the configured threshold is ‘T’, then each core checks for a per-core threshold value ‘T/n’. If there are ‘n’ nodes in a clustered system, and the configured threshold is ‘T’, then each node checks for a per-node threshold value ‘T/n’. According to the pigeonhole principle, if an entity has reached or exceeded the threshold ‘T’, then the entity must have reached or exceeded a value of ‘T/n’ on at least one core or node. Upon the entity crossing a ‘T/n’ value on any core or node, the core or node informs snmpd about this entity. Snmpd then gathers information about this entity from all the cores and checks for the threshold ‘T’. | 10-17-2013 |
20130339503 | SYSTEMS AND METHODS FOR SUPPORTING A SNMP REQUEST OVER A CLUSTER - The present disclosure is directed towards systems and methods for supporting Simple Network Management Protocol (SNMP) request operations over clustered networking devices. The system includes a cluster that includes a plurality of intermediary devices and an SNMP agent executing on a first intermediary device of the plurality of intermediary devices. The SNMP agent receives an SNMP GETNEXT request for an entity. Responsive to receipt of the SNMP GETNEXT request, the SNMP agent requests a next entity from each intermediary device of the plurality of intermediary devices of the cluster. To respond to the SNMP request, the SNMP agent selects a lexicographically minimum entity. The SNMP agent may select the lexicographically minimum entity from a plurality of next entities received via responses from each intermediary device of the plurality of intermediary devices. | 12-19-2013 |
20150222475 | SYSTEMS AND METHODS FOR SUPPORTING A SNMP REQUEST OVER A CLUSTER - The present disclosure is directed towards systems and methods for supporting Simple Network Management Protocol (SNMP) request operations over clustered networking devices. The system includes a cluster that includes a plurality of intermediary devices and an SNMP agent executing on a first intermediary device of the plurality of intermediary devices. The SNMP agent receives an SNMP GETNEXT request for an entity. Responsive to receipt of the SNMP GETNEXT request, the SNMP agent requests a next entity from each intermediary device of the plurality of intermediary devices of the cluster. To respond to the SNMP request, the SNMP agent selects a lexicographically minimum entity. The SNMP agent may select the lexicographically minimum entity from a plurality of next entities received via responses from each intermediary device of the plurality of intermediary devices. | 08-06-2015 |