Patent application number | Description | Published |
20080291753 | Semiconductor memory device and latency signal generating method thereof - A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal. | 11-27-2008 |
20100271886 | Semiconductor memory device and latency signal generating method thereof - A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal. | 10-28-2010 |
20110208988 | Latency signal generator and method thereof - A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals. | 08-25-2011 |
20130227344 | DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE - Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device. | 08-29-2013 |
20130242635 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SENSING VERIFICATION UNIT - A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit. | 09-19-2013 |
20130294140 | ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal. | 11-07-2013 |
20130322149 | MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE - A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively. | 12-05-2013 |
20140104921 | SEMICONDUCTOR MEMORY DEVICE HAVING OTP CELL ARRAY - Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node. | 04-17-2014 |