Patent application number | Description | Published |
20080229011 | CACHE MEMORY UNIT AND PROCESSING APPARATUS HAVING CACHE MEMORY UNIT, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - A cache memory unit connecting to a main memory system having a cache memory area in which, if memory data that the main memory system has is registered therewith, the registered memory data is accessed by a memory access instruction that accesses the main memory system and a local memory area with which local data to be used by the processing section is registered and in which the registered local data is accessed by a local memory access instruction, which is different from the memory access instruction. | 09-18-2008 |
20080293112 | SUCCINIC ACID-PRODUCING BACTERIUM AND PROCESS FOR PRODUCING SUCCINIC ACID - Coryneform bacterium is modified so that an activity of acetyl-CoA hydrolase is decreased, and succinic acid is produced by using the bacterium. | 11-27-2008 |
20080301368 | Recording controller and recording control method - Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline. | 12-04-2008 |
20080301372 | Memory access control apparatus and memory access control method - A memory access control apparatus includes an MIB for storing information on a plurality of requests and processing the requests in parallel. Upon receipt of a memory access request, the MIB selects a request for a data block to be processed corresponding to the same set of a data block to be processed in response to the memory access request, and outputs a WAY assigned to the selected request to a replace-WAY selecting unit. The replace-WAY selecting unit excludes the WAY output from the MIB, and selects a WAY to be assigned to the memory access request based on a predetermined algorithm. | 12-04-2008 |
20080313405 | Coherency maintaining device and coherency maintaining method - A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit. | 12-18-2008 |
20080320256 | LRU control apparatus, LRU control method, and computer program product - To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data | 12-25-2008 |
20090013105 | Request control apparatus and request control method - A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source. | 01-08-2009 |
20090300287 | Method and apparatus for controlling cache memory - An apparatus for controlling a cache memory that stores therein data transferred from a main storing unit includes a computing processing unit that executes a computing process using data, a connecting unit that connects an input portion and an output portion of the cache memory, a control unit that causes data in the main storing unit to be transferred to the output portion of the cache memory through the connecting unit when the data in the main storing unit is input from the input portion of the cache memory into the cache memory, and a transferring unit that transfers data transferred by the control unit to the output portion of the cache memory, to the computing processing unit. | 12-03-2009 |
20100332758 | Cache memory device, processor, and processing method - A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit. | 12-30-2010 |
20110072212 | CACHE MEMORY CONTROL APPARATUS AND CACHE MEMORY CONTROL METHOD - A cache memory controller searches a second cache tag memory holding a cache state information indicating whether any of multi-processor cores storing a registered address of information registered within its own first cache memory exists. When a target address coincides with the obtained registered address, the cache memory controller determines whether an invalidation request or a data request to a processor core including a block is necessary based on the cache status information. Once it is determined that invalidation or a data request for the processor including the block, the cache memory controller determines whether a retry of instruction based on a comparison result of the first cache tag memory is necessary, if it is determined that invalidation or a data request for the processor including the block. | 03-24-2011 |
20110087841 | PROCESSOR AND CONTROL METHOD - A processor includes a first processing unit that has a first memory and performs processing, a second processing unit that performs processing, a second memory that holds status information specifying a status of data held in the first memory, and a control unit that outputs a request for reading out the data of the first address to the first processing unit upon receiving a first access request for data of a first address from the second processing unit when first status information of the data of the first address indicates that the data of the first address is held in the first memory in an exclusive state or an owned state and that allows the second processing unit to access data of the first address included at the second memory upon receiving a no-data-modification notification indicating the data of the first address is not modified by the first processing unit. | 04-14-2011 |
20140068179 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD - A processor includes a cache memory that holds data from a main storage device. The processor includes a first control unit that controls acquisition of data, and that outputs an input/output request that requests the transfer of the target data. The processor includes a second control unit that controls the cache memory, that determines, when an instruction to transfer the target data and a response output by the first processor on the basis of the input/output request that has been output to the first processor is received, whether the destination of the response is the processor, and that outputs, to the first control unit when the second control unit determines that the destination of the response is the processor, the response and the target data with respect to the input/output request. | 03-06-2014 |
20140289469 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes: processing units, each including a first cache memory; a second cache memory being shared among the processing units; an acquiring unit to acquire lock target information including first storage location information in an first cache memory included in one of the processing units from an access request to data cached in the second cache memory; a retaining unit to retain the lock target information until an response processing to the access request is completed; and a control unit to control an access request to the second cache memory, the access request being related to a replace request to a first cache memory, based on second storage location information of replace target data in the first cache memory and the lock target information, the second storage location information acquired from the access request related to the replace request. | 09-25-2014 |
20140331013 | ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD OF ARITHMETIC PROCESSING APPARATUS - An arithmetic processing apparatus according to one embodiment of the present invention includes: a plurality of arithmetic processing units configured to perform arithmetic operations to output access requests; a cache memory to retain data undergoing the arithmetic processes of the arithmetic processing units in cache blocks; a retaining unit configured to retain a control target address specifying a control target cache block and control target identifying information specifying an arithmetic processing unit of a control target access requester; and a control unit configured to control an access request for the cache block specified by the control target address and the control target identifying information on the basis of an access target address contained in an access request issued by any one of the arithmetic processing units and requester identifying information specifying the arithmetic processing unit having issued the access request. | 11-06-2014 |