Patent application number | Description | Published |
20090016133 | SEMICONDUCTOR MEMORY AND SYSTEM - A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies a voltage difference of a node pair after the operation start of the word line driving circuit. A switch circuit is provided between the bit line pair and the node pair. The switch circuit has coupled the access side of the bit line pair to an access side of the node pair at an instant of the operation start of the word line driving circuit, and has separated a non-access side of the bit line pair from a non-access side of the node pair at an instant of operation start of the sense amplifier. | 01-15-2009 |
20090027980 | SEMICONDUCTOR MEMORY - Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect. | 01-29-2009 |
20090027982 | SEMICONDUCTOR MEMORY AND TEST SYSTEM - A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal from a test apparatus. A dummy defect output unit outputs a dummy defect signal during a predetermined period of time after the defect detection input unit receives the defect detection signal. A data output unit inverts a logic of the read data output from the read unit during an activation of the dummy defect signal. Accordingly, an artificial defect can be generated by the semiconductor memory without changing the test apparatus or a test program. As a result of this, a relief efficiency can be enhanced and a test cost can be reduced. | 01-29-2009 |
20090040849 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized. | 02-12-2009 |
20090161469 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM - The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on receipt of the first input signal, and that outputs the second output signal based on a check signal; a third buffer circuit that outputs a third output signal based on the check signal; a determination circuit that receives the second output signal and the third output signal and activates a detection signal, in response to the detection that the second output signal is behind the third output signal; and a fourth buffer circuit that operates during the activation of the detection signal and outputs the third output signal to the output terminal, on receipt of the first input signal. | 06-25-2009 |
20090204358 | SEMICONDUCTOR INTEGRATED CIRCUIT - A temperature detector sets the level of a temperature detecting signal to a level indicating a high temperature state, detecting that the chip temperature is higher than a first boundary temperature. The temperature detector sets the level of thereof to a level indicating a low temperature state, detecting that the chip temperature is lower than a second boundary temperature. A control circuit changes its operating state according to the level of the temperature detecting signal. This prevents the operating state of the control circuit from frequently switched even when the chip temperature fluctuates around the boundary temperatures, and accordingly reduces current consumption of the control circuit due to the switching operation. Further, the first and second boundary temperatures set a buffer zone, so that the temperature detector does not detect power supply noises as temperature variation. This can prevent malfunction of the temperature detector and the semiconductor integrated circuit. | 08-13-2009 |
20100091594 | SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on. | 04-15-2010 |
20100110809 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM WITH REDUNDANT ELEMENT - A semiconductor memory device includes a memory cell array, a redundant element, an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal, a decoder circuit configured to select the redundant element in response to an externally applied address that matches the redundancy address selected by the address specifying circuit, and a test mode setting circuit configured to change the switchover signal in response to an externally applied input, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses. | 05-06-2010 |
20100110810 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals, and a refresh-target selecting circuit configured to successively select all the primary word lines and all the one or more redundant word lines one by one in response to the respective pulses of the refresh timing signal, wherein a refresh operation is performed with respect to the word lines that are successively selected by the refresh-target selecting circuit. | 05-06-2010 |
20100142250 | SEMICONDUCTOR MEMORY AND SYSTEM - A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines when one of the access control circuits is used, and swaps the connections between a pair of data terminals and a pair of data lines when the other one of the access control circuits is used. Accordingly, it is possible to give a data signal at the same logic level to bit lines with different logics from each other. Stress can be given between a contact arranged between a pair of the access control circuits and bit lines adjacent to both sides of the contact. Consequently, designing of a test pattern can be simplified, and test efficiency can be improved. | 06-10-2010 |
20120128202 | Image processing apparatus, image processing method and computer readable information recording medium - An image processing apparatus includes an obtaining part configured to obtain a plurality of images including a photographing object photographed by a photographing part; a determination part configured to detects a shift in position between a first image and a second image included in the plurality of images obtained by the obtaining part, and determine whether the first image is suitable for being superposed to the second image; a selection part configured to select a certain number of images from the plurality of images based on a determination result of the determination part; and a synthesis part configured to synthesize the certain number of images selected by the selection part. | 05-24-2012 |
20120195145 | SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM A SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on. | 08-02-2012 |
20120249826 | IMAGE SELECTION DEVICE AND IMAGE SELECTING METHOD - An image selection device includes: an image acquiring unit which acquires a plurality of shot images acquired by continuously shooting a subject; an area segmentation unit which segments an image area of the shot image into a motion area indicating different positions by a specified amount or more between two shot images and a non-motion area other than the motion area based on the two consecutive shot images in time series in the plurality of shot images; and a selection unit which selects at least one shot image from the plurality of shot images based on an amount of blur of an image in the non-motion area. | 10-04-2012 |
20130136364 | IMAGE COMBINING DEVICE AND METHOD AND STORAGE MEDIUM STORING IMAGE COMBINING PROGRAM - A device that combines a first image photographed with a first amount of exposure and a second image photographed with a second amount of exposure lower than the first amount of exposure, thereby generating a combined image having a wider dynamic range than a dynamic range for the amounts of exposure of the first and second images, the device includes a motion region extraction unit configured to extract at least one motion region in which an object moving between the first image and the second image is shown; a combining ratio determining unit configured to increase a combining ratio of the second image to the first image for a pixel in a background region outside of the at least one motion region such that the higher a luminance value of a pixel of the first image, the higher the combining ratio. | 05-30-2013 |