Patent application number | Description | Published |
20100088445 | DATA PROCESSING SYSTEM AND SEMICONDUTOR INTEGRATED CIRCUIT - The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened. In addition, since the interrupting process in the single central processing unit is not necessary, interruption response of another central processing unit is increased. | 04-08-2010 |
20100182848 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. | 07-22-2010 |
20110314323 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. | 12-22-2011 |
20130073765 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal. | 03-21-2013 |
20130147991 | SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD - An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction. | 06-13-2013 |
20130287319 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND IMAGE PROCESSING METHOD - A semiconductor device | 10-31-2013 |
20150049219 | SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD - An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction. | 02-19-2015 |
20160110842 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND IMAGE PROCESSING METHOD - A semiconductor device | 04-21-2016 |