Patent application number | Description | Published |
20080201553 | NON-VOLATILE MEMORY SYSTEM - This non-volatile memory system includes: a non-volatile memory; and a memory controller controlling read and write of the non-volatile memory. Access control of the non-volatile memory system is performed in accordance with a logical address, using an address translation table within the memory controller that is updated in association with data write and that indicates a correlation between logical addresses provided by a host and physical addresses of the non-volatile memory. The non-volatile memory system is also configured to be able to set a system configuration and function in relation to the host. | 08-21-2008 |
20080244349 | MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory. | 10-02-2008 |
20080270072 | DATA REMAINING PERIOD MANAGEMENT DEVICE AND METHOD - A remaining period management device according to an example of the invention comprises a statistic calculation unit that measures sampling data associated with monitoring target data stored in a storage device having a finite data remaining period and calculates sampling statistical data based on a measurement result of the sampling data, and a remaining period detection unit that obtains remaining period data indicative of a data remaining period of the monitoring target data based on predetermined remaining period characteristic data indicative of a characteristic that statistical data varies with elapse of data remaining period and the sampling statistical data calculated by the statistic calculation unit. | 10-30-2008 |
20090109749 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2 | 04-30-2009 |
20090141552 | MEMORY SYSTEM - A memory system includes a nonvolatile memory including a plurality of memory cells, each memory cell being configured to store n levels (n is a natural number of not less than 3) in accordance with a threshold voltage, and a converter which encodes input data in the form of a bit string, records the encoded data in the nonvolatile memory, and limits a difference between levels which adjacent memory cells can take to not more than a predetermined level lower than the n levels. | 06-04-2009 |
20090190399 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY - In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level. | 07-30-2009 |
20090193183 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 07-30-2009 |
20090241012 | MEMORY CONTROLLER - A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line. | 09-24-2009 |
20090244974 | MEMORY SYSTEM AND DATA WRITING METHOD - A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller. | 10-01-2009 |
20090307414 | MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS - A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit configured to duplicate input data by assigning the input data to a predetermined threshold level and another threshold level different from the predetermined threshold level. Moreover, the memory system includes a controller configured to control to store the data duplicated by the duplicating-converting circuit, in the NAND-type flash memory. | 12-10-2009 |
20100049990 | STORAGE DEVICE AND RECORDING AND REPRODUCING SYSTEM - A storage device includes a decryption section, non-volatile memory, and an encryption section. The decryption section decrypts externally input encrypted data. The non-volatile memory records data decrypted by the decryption section. The encryption section encrypts and outputs decrypted data read out from the non-volatile memory. | 02-25-2010 |
20100097864 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 04-22-2010 |
20100199082 | MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory. | 08-05-2010 |
20100217919 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state. | 08-26-2010 |
20100245623 | STILL IMAGE MEMORY DEVICE AND LIGHTING APPARATUS - A still image memory device includes an imaging unit, a nonvolatile memory unit that includes a first memory area and a second memory area, and a control unit that controls the nonvolatile memory unit. The control unit includes a first processing unit that stores, in the first memory area, the image data output from the imaging unit; a second processing unit that, based on memory status of the first memory area, reads and compresses image data selected from a plurality of image data stored in the first memory area, stores compressed image data in the second memory area, and destroys the image data selected from the plurality of image data stored in the first memory area; and a third processing unit that, based on memory status of the second memory area, destroys compressed image data selected from a plurality of compressed image data stored in the second memory area. | 09-30-2010 |
20100251075 | MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS - A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data. | 09-30-2010 |
20110131470 | MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area. | 06-02-2011 |
20110238890 | MEMORY CONTROLLER, MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory controller that performs control of a nonvolatile semiconductor memory includes a first management table that stores correspondence between logical block addresses and physical block addresses, a second management table that stores a number of times of data writing for each of the logical block addresses, and a third management table that stores a number of times of data erasing for each of the physical block addresses. The memory controller according to the embodiment includes a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block. The writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks. | 09-29-2011 |
20110246791 | MEMORY CHIP, INFORMATION STORING SYSTEM, AND READING DEVICE - According to one embodiment, a memory chip, which is connected to a writing device that writes data and to a reading device that reads data, includes: a memory including a first area that is a predetermined data storage area; a second encryption key generating unit that receives second key information stored in the reading device and generates a third key; and a sending unit that transmits, to the reading device, second encrypted data obtained by encrypting data stored in the memory using the third key. The second encrypted data is received by the reading device and is decrypted by using a fourth key that is stored in the reading device and that corresponds to the third key. | 10-06-2011 |
20110296278 | MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory. | 12-01-2011 |
20120162474 | CARD-SHAPED ELECTRONIC DEVICE, COMMUNICATION TERMINAL AND AUTHENTICATION METHOD - A memory card of an embodiment has an external connection terminal configured to be connected to a card connection terminal of a digital camera having an image pickup unit, a communication unit configured to transmit and receive data wirelessly to and from another digital camera, an image recognition unit configured to extract a characteristic from a recognition image, and a CPU configured to permit subsequent transmission and reception of data to and from the other digital camera when a characteristic of a first recognition image photographed by the image pickup unit and a characteristic of a second recognition image transmitted from the other digital camera correspond to each other. | 06-28-2012 |
20120206977 | SEMICONDUCTOR MEMORY SYSTEM CAPABLE OF SUPPRESSING CONSUMPTION CURRENT - According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices discharges electric charge, the other of the first and second semiconductor memory devices receives the discharged electric charge through the wiring line. | 08-16-2012 |
20120250408 | MEMORY SYSTEM, CONTROLLER, AND METHOD FOR CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system of the embodiment includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host. | 10-04-2012 |
20120266045 | MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory. | 10-18-2012 |
20130080683 | MEMORY SYSTEM PROVIDED WITH NAND FLASH MEMORY AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory system includes first, and second districts, and control section. Each of the first and second districts includes a memory cell array. The control section receives a write command to simultaneously write first data to the first, and second districts, and addresses, and simultaneously writes the first data to the first and second districts. | 03-28-2013 |
20130227268 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section. | 08-29-2013 |
20130243274 | Person Image Processing Apparatus and Person Image Processing Method - According to one embodiment, a person image processing apparatus includes: an input processor configured to input a plurality of pieces of image data captured at different times by an image capture module; an extraction module configured to extract a person display area showing a same person from each of the pieces of image data captured at the different times; a feature detector configured to detect a feature point showing a feature of a part of a person from the person display area extracted from each of the pieces of image data and acquire reliability of the part shown in the feature point; and a correction module configured to, when correcting the person display area subjected to input processing by the input processor, perform weighting based on the reliability of the feature point included in the person display area. | 09-19-2013 |
20130290738 | MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area. | 10-31-2013 |
20140063952 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group. | 03-06-2014 |
20140071756 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER - According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect. | 03-13-2014 |
20140281157 | MEMORY SYSTEM, MEMORY CONTROLLER AND METHOD - According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip. The memory controller causes at least two memory chips to store the same correspondence relation information. Further, in the read operation, the memory controller reads the correspondence relation information from at least one memory chip among the plurality of memory chips storing the same correspondence relation information. | 09-18-2014 |
20140298043 | MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area. | 10-02-2014 |
20140369127 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data. | 12-18-2014 |
20150036430 | SEMICONDUCTOR MEMORY DEVICE - A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong. | 02-05-2015 |
20150036434 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data. | 02-05-2015 |