# Hironori Uchikawa, Fujisawa-Shi JP

## Hironori Uchikawa, Fujisawa-Shi JP

Patent application number | Description | Published |
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20110038212 | CONTROLLER AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum. | 02-17-2011 |

20120066563 | ERROR CORRECTION DECODER, MEMORY CONTROLLER AND RECEIVER - According to an embodiment, an error correction decoder carries out iterative decoding for data coded using an irregular LDPC code. The decoder includes a likelihood control unit. The likelihood control unit is configured to carry out weighting using first extrinsic value weights when a first condition including a condition that a code word cannot be obtained even when number of times the iterative decoding has been carried out is greater than a first iterative times, in order to increase absolute value of a extrinsic value from a check node not satisfying a parity check to a variable node, wherein the first extrinsic value weights are equal to each other or become larger in descending order of column weights of the variable nodes, and a maximum of the first extrinsic value weights is not equal to a minimum of the first extrinsic value weights. | 03-15-2012 |

20120226954 | ERROR CORRECTION DECODER AND STORAGE APPARATUS - According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion. | 09-06-2012 |

20120240008 | ENCODER AND STORAGE APPARATUS - According to an embodiment, an encoder has a storage and a generator. The storage stores information indicative of a generator matrix corresponding to a partial parity check matrix in a rank-deficient parity check matrix including a lower triangular matrix and one or more cyclic matrices or zero matrices, the partial parity check matrix including rows different from rows of the lower triangular matrix. The generator carries out semi-systematic coding using the generator matrix to generate a portion of code word. The generator matrix has a cyclic matrix portion with one or more cyclic matrices and a non-cyclic matrix portion with rows number of which is equal to a degree of rank deficiency in the partial parity check matrix. | 09-20-2012 |

20130055050 | ERROR CORRECTION ENCODING APPARATUS, ERROR CORRECTION DECODING APPARATUS, NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM, AND PARITY CHECK MATRIX GENERATION METHOD - According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification. | 02-28-2013 |

20130227372 | ENCODING APPARATUS AND COMMUNICATION APPARATUS - According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type. | 08-29-2013 |

20130254633 | DECODER, DECODING METHOD AND COMMUNICATION APPARATUS - According to one embodiment, a decoder includes a control unit and a decoding unit. The control unit determines a window size applied to a first target frame to be a first value and determines a window size applied to a second target frame different from the first target frame to be a second value different from the first value. The decoding unit carries out windowed decoding of a spatially coupled code on the first target frame with the window size set to the first value and carries out windowed decoding of a spatially coupled code on the second target frame with the window size set to the second value. | 09-26-2013 |

20140019819 | RECEIVER AND RECEIVING METHOD - According to an embodiment, a receiver includes a generation unit and a scheduler. The generation unit generates a convergence indicator for evaluating a convergence status of the iterative decoding process based on reliability information. The scheduler controls execution of local iteration includes the iterative decoding process terminates and controls execution of global iteration includes alternation between a symbol de-mapping process and an iterative decoding process, based on the convergence indicator. | 01-16-2014 |

20140223263 | CONTROLLER - According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix. | 08-07-2014 |

20140289583 | DECODING APPARATUS, DECODING METHOD, AND DECODING PROGRAM - According to one embodiment, a decoding apparatus includes first and second acquisition units, a holding unit, a calculation unit, and a decision unit. The first acquisition unit acquires first measurement values of measurements performed to measure an eigenvalue of an encoded Z operator to a first encoded qubit of the two encoded qubits. The second acquisition unit acquires second measurement values of measurements performed to measure an eigenvalue of an encoded X operator to a second encoded qubit of the two encoded qubits. The holding unit holds error probabilities for the first measurement values and the second measurement values. The calculation unit calculates probabilities for measurement values of an encoded Bell measurement by using the first measurement values, the second measurement values, and the error probabilities. The decision unit decides measurement values of the encoded Bell measurement, based on the calculated probabilities. | 09-25-2014 |