Patent application number | Description | Published |
20090258446 | PATTERN VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIA - A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not. | 10-15-2009 |
20090258503 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM - A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps. | 10-15-2009 |
20100003819 | DESIGN LAYOUT DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total peripheral length of the patterns formed on the wafer when the patterns corresponding to the design layout are formed on the wafer is pattern peripheral length within a predetermined range. | 01-07-2010 |
20100035168 | PATTERN PREDICTING METHOD, RECORDING MEDIA AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A pattern predicting method according to one embodiment includes obtaining shape data of a target pattern from shape data of a second pattern to be formed by transferring a first pattern at predetermined process conditions by using a first neutral network, the target pattern being to be a target of the second pattern when the first pattern is transferred at the predetermined process conditions, so as to keep the transferred patterns within an acceptable range, the transferred patterns being formed by transferring the first pattern at process conditions changed from the predetermined process conditions and obtaining shape data of a new first pattern for forming the target pattern at the predetermined process conditions by using a second neutral network. | 02-11-2010 |
20100038795 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern. | 02-18-2010 |
20100185313 | PATTERN DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern. | 07-22-2010 |
20100190342 | PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, COMPUTER PROGRAM PRODUCT, AND PATTERN-SHAPE-DETERMINATION-PARAMETER GENERATING METHOD - A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance. | 07-29-2010 |
20100216064 | SEMICONDUCTOR-DEVICE MANUFACTURING METHOD, COMPUTER PROGRAM PRODUCT, AND EXPOSURE-PARAMETER CREATING METHOD - A semiconductor-device manufacturing method includes: correcting a systematic component of process proximity effect, which occurs in a process other than exposure processing to thereby set a target pattern after exposure; adjusting an exposure parameter such that a difference between a dimension of the target pattern and a pattern dimension after the exposure is within tolerance; and forming, when an exposure margin calculated from the exposure parameter by using the exposure the random component of fluctuation in the process proximity effect is within the tolerance, a pattern on a semiconductor substrate with the adjusted exposure parameter. | 08-26-2010 |
20100241261 | PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT - Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result. | 09-23-2010 |
20110047518 | PATTERN DETERMINING METHOD - According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area. | 02-24-2011 |
20110065030 | MASK PATTERN DETERMINING METHOD, MASK MANUFACTURING METHOD, AND DEVICE MANUFACTURING METHOD - According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship. | 03-17-2011 |
20110307845 | PATTERN DIMENSION CALCULATION METHOD AND COMPUTER PROGRAM PRODUCT - A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position. | 12-15-2011 |
20120184109 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM - A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps. | 07-19-2012 |
20120244707 | METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value. | 09-27-2012 |
20120246601 | PATTERN CORRECTING METHOD, MASK FORMING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area. | 09-27-2012 |
20130063707 | PATTERN GENERATING METHOD, PATTERN FORMING METHOD, AND PATTERN GENERATING PROGRAM - One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern. | 03-14-2013 |
20140059502 | PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD - According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected. | 02-27-2014 |