Patent application number | Description | Published |
20100120790 | DPP-IV INHIBITOR INCLUDING BETA-AMINO GROUP, PREPARATION METHOD THEREOF AND PHARMACEUTICAL COMPOSITION CONTAINING THE SAME FOR PREVENTING AND TREATING DIABETES OR OBESITY - The present invention provides a novel heterocyclic compound containing a beta-amino group, a method for preparing the same, and a pharmaceutical composition comprising the same heterocyclic compound or a pharmaceutically acceptable salt thereof as an active ingredient. The heterocyclic compound of the present invention exhibits excellent DPP-IV inhibitory activity and bioavailability and therefore can be useful for the prophylaxis or treatment of DPP-IV-related diseases such as diabetes or obesity. | 05-13-2010 |
20110201624 | Pharmaceutical Composition for Prevention and Treatment of Diabetes or Obesity Comprising a Compound that Inhibits Activity of Dipeptidyl Peptidase-IV, and other Antidiabetic or Antiobesity Agents as Active Ingredients - The present invention relates to a pharmaceutical composition for the prevention and treatment of diabetes or obesity comprising as active ingredients a compound which inhibits the activity of dipeptidyl peptidase-IV (DPP-IV), a pharmaceutically acceptable salt thereof, a hydrate thereof, or a solvate thereof, and one or more other antidiabetic or antiobesity agents. The pharmaceutical composition exhibits excellent glucose tolerance and may be useful in the prevention and treatment of diabetes, obesity, and the like by effectively inhibiting blood glucose levels and reducing fat mass. | 08-18-2011 |
20120016125 | METHOD FOR PREPARING DIPEPTIDYL PEPTIDASE-IV INHIBITOR AND INTERMEDIATE - The present invention relates to an improved method for preparing dipeptidyl peptidase-IV inhibitor and intermediate. The present invention is able to reduce preparation costs by using low cost reagents on reaction and is able to be used in mass production by improving yield. | 01-19-2012 |
20120016126 | METHOD FOR MANUFACTURING DIPEPTIDYL PEPTIDASE-IV INHIBITOR AND INTERMEDIATE - The present invention relates to an improved method for manufacturing dipeptidyl peptidase-IV inhibitor and intermediate. The present invention allows reduction of production costs by reacting low cost reagents, improves yield and is adaptable for mass production. | 01-19-2012 |
20130072459 | PHARMACEUTICAL COMPOSITION FOR THE PREVENTION OR THE TREATMENT OF NON-ALCOHOLIC FATTY LIVER DISEASE AND THE METHOD FOR PREVENTION OR TREATMENT OF NON-ALCOHOLIC FATTY LIVER DISEASE USING THE SAME - The present invention provides a pharmaceutical composition for the prevention and treatment of a non-alcoholic fatty liver disease (NAFLD), containing an active ingredient selected from the group consisting of Compound 1 represented by formula 1, sitagliptin, vildagliptin, linagliptin or a pharmaceutically acceptable salt thereof. Further, the present invention provides a method for the prevention or treatment of a non-alcoholic fatty liver disease, including administering an effective amount of an active ingredient selected from the group consisting of Compound 1 represented by formula 1, sitagliptin, vildagliptin, linagliptin or a pharmaceutically acceptable salt thereof to a mammal including a human in need thereof. Further, the present invention provides use of Compound 1 represented by formula 1, sitagliptin, vildagliptin, linagliptin or a pharmaceutically acceptable salt thereof, for manufacturing a pharmaceutical composition for the prevention or treatment of a non-alcoholic fatty liver disease. | 03-21-2013 |
Patent application number | Description | Published |
20090265953 | LAUNDRY DRYER AND METHOD FOR CONTROLLING THE SAME - The present invention relates to a dryer and a method for controlling the same. The method for controlling a dryer includes a steam supply step for supplying steam generated in a steam generator to a dram, and a hot air supply step for supply hot air generated in a hot air heater to the drum. The method according to the present invention has an advantageous effect of removing wrinkles efficiently. | 10-29-2009 |
20090307921 | LAUNDRY DRYER AND METHOD FOR CONTROLLING THE SAME - A laundry dryer and a method for controlling the same capable of removing or preventing wrinkles or creases of clothes and the like are disclosed. The laundry dryer includes a selectively rotatable drum, a hot air heater which heats air to supply hot air having a high temperature into the drum, a steam generator which generates steam to supply the steam into the drum, and a safety valve which discharges the steam to an outside when steam flow is interrupted. | 12-17-2009 |
20100095716 | Laundry machine - The present invention relates to steam dryers, and more specifically, the present invention relates to a steam dryer for removing creases or crumples from, or preventing the same from forming on, clothes. The steam dryer includes a drum ( | 04-22-2010 |
Patent application number | Description | Published |
20100155818 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 06-24-2010 |
20130109165 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE TRANSISTOR | 05-02-2013 |
20130161832 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines. | 06-27-2013 |
20130175603 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 07-11-2013 |
20130320433 | VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes. | 12-05-2013 |
20140021485 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area. | 01-23-2014 |
20140024214 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate. | 01-23-2014 |
20140061572 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This technology relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include a line layer formed over a substrate, and connection structures each configured to include a first metal layer pattern, a barrier layer pattern, and a second metal layer pattern sequentially stacked over the line layer, for bonding another substrate to the substrate. In accordance with this technology, abnormal silicidation may be prevented because the barrier layer is formed at the bonding interface of the substrates, and the bonding energy of the substrates may be improved by titanium (Ti)-silicon (Si) bonding. | 03-06-2014 |
20140061746 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines. | 03-06-2014 |
20140061850 | SEMICONDUCTOR DEVICE WITH BURIED BITLINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls. | 03-06-2014 |
20140097519 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer. | 04-10-2014 |
20140232014 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines. | 08-21-2014 |
20150031180 | VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes. | 01-29-2015 |