Hess, CA
Bee Hess, Valencia, CA US
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20100160740 | Use of Patterns in a Therapy Management System - A method of diabetes analysis includes obtaining average glucose level information for a time period over a plurality of days. A current event occurrence is determined. An event occurrence in the average glucose level information within the time period corresponding to the current event occurrence is determined, where the current event occurrence is at a different time of day than the event occurrence. The average glucose level information starting in time from the event occurrence within the time period is analyzed. A notification event in the average glucose level information starting in time from the event occurrence within the time period is determined. A current notification event in time from the current event occurrence is predicted based on a time span from the event occurrence to the notification event in the average glucose level information. An action is initiated in advance of the predicted current notification event. | 06-24-2010 |
20100161236 | Pattern Recognition and Filtering in a Therapy Management System - A method of diabetes analysis includes receiving a plurality of glucose level readings for a user. A common event occurrence in at least two of the glucose level readings is determined. The at least two glucose level readings from the common event occurrence onwards in time for a time period is analyzed. A glucose level pattern formed by the at least two glucose level readings having a similar shape is determined. At least one anomalous glucose level reading having the similar shape and not conforming to the glucose level pattern is analyzed. The at least one anomalous glucose level reading is adapted to the pattern to form an adapted glucose level pattern. An insulin dosage for the time period beginning at the common event occurrence is calculated based on the adapted glucose level pattern. | 06-24-2010 |
Carl Hess, Los Altos, CA US
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20120086799 | FOCUS OFFSET CONTAMINATION INSPECTION - A system and method for detecting defects on a reticle is disclosed. The method may comprise determining a best focus setting for imaging the reticle; obtaining a first image of the reticle, the first image obtained at the best focus setting plus a predetermined offset; obtaining a second image of the reticle, the second image obtained at the best focus setting minus the predetermined offset; generating a differential image, the differential image representing a difference between the first image and the second image; and identifying a defect on the reticle based on the differential image. The method in accordance with the present disclosure may also be utilized for detecting defects on at least a portion of the reticle. | 04-12-2012 |
20130111417 | Database-Driven Cell-to-Cell Reticle Inspection | 05-02-2013 |
20130279792 | Method and System for Hybrid Reticle Inspection - A semiconductor inspection apparatus performs a hybrid inspection process including cell-to-cell inspection, die-to-die inspection and die-to-golden or die-to-database inspection. The apparatus creates a golden image of a reticle complimentary to portions of the reticle that can be inspected by cell-to-cell inspection or die-to-die inspection. Alternatively, the apparatus creates a reduced database complimentary to portions of the reticle that can be inspected by cell-to-cell inspection or die-to-die inspection. | 10-24-2013 |
20150178914 | Methods and Systems for Inspection of Wafers and Reticles Using Designer Intent Data - Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer. | 06-25-2015 |
Carl Hess, Loss Altos, CA US
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20110276935 | SYSTEMS AND METHODS FOR DETECTING DESIGN AND PROCESS DEFECTS ON A WAFER, REVIEWING DEFECTS ON A WAFER, SELECTING ONE OR MORE FEATURES WITHIN A DESIGN FOR USE AS PROCESS MONITORING FEATURES, OR SOME COMBINATION THEREOF - Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. | 11-10-2011 |
Carl E. Hess, Los Altos, CA US
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20090310136 | Method for Detection of Oversized Sub-Resolution Assist Features - Disclosed are methods and apparatus for inspecting a sub-resolution assist features (SRAF) on a reticle. A test flux measurement for a boundary area that encompasses a width and a length portion of a test SRAF is determined, and at least one reference flux measurement for one or more boundary areas of one or more reference SRAF's is determined. The test flux measurement is compared with the reference flux measurements. The comparison is used to then determine whether the test SRAF is undersized or oversized. If the test SRAF is determined to be oversized, it may then be determined whether the test SRAF is defective based on the comparison using a first threshold | 12-17-2009 |
20130211736 | TIME-VARYING INTENSITY MAP GENERATION FOR RETICLES - An optical reticle inspection tool is used during a first inspection to obtain, for each set of one or more patch areas of the reticle, a reference average of multiple reference intensity values corresponding to light measured from sub-areas of each patch area. After using the reticle in photolithography processes, the optical reticle inspection tool is used during a second inspection to obtain, for each set of one or more patch areas, an average of multiple test intensity values corresponding to light measured from the of sub-areas. The first and second inspections use the same tool setup recipe. A difference intensity map is generated, and such map comprises map values that each corresponds to a difference between each average of the test and reference intensity values for each set of one or more patches. The difference intensity map indicates whether the reticle has degraded over time more than a predefined level. | 08-15-2013 |
20140168418 | DELTA DIE INTENSITY MAP MEASUREMENT - With an optical inspection tool, images of a plurality of patches of a plurality of dies of a reticle are obtained. The patch images are obtained so that each patch image is positioned relative to a same reference position within its respective die as another die-equivalent one of the patch images in each the other ones of the dies. For each patch image, an integrated value is determined for an image characteristic of sub-portions of such patch image. For each patch image, a reference value is determined based on the integrated values of the patch image's corresponding die-equivalent patch images. For each patch image, a difference between that patch image's integrated value and an average or median value of its die-equivalent patch images is determined whereby a significant difference indicates a variance in a pattern characteristic of a patch and an average or median pattern characteristic of its die-equivalent patches. | 06-19-2014 |
20150103351 | USING REFLECTED AND TRANSMISSION MAPS TO DETECT RETICLE DEGRADATION - An optical reticle inspection tool is used during an inspection to obtain, for each local area, an average of multiple reflected intensity values corresponding to light reflected from a plurality of sub-areas of each local area of the reticle. The optical reticle inspection tool is also used during the inspection to obtain, for each local area, an average of multiple transmitted intensity values corresponding to light transmitted through the sub-areas of each local area of the reticle. A combined intensity map is generated by combining, for each local area, the average of multiple reflected intensity values and the average of multiple transmitted intensity values such that a reticle pattern of the reticle is cancelled from the combined intensity map if the reticle has not degraded and such that the reticle pattern of the reticle is not cancelled out of the combined intensity map if the reticle has degraded. | 04-16-2015 |
20150276617 | DELTA DIE AND DELTA DATABASE INSPECTION - Disclosed are methods and apparatus for inspecting a photolithographic reticle. An inspection tool is used to obtain a plurality of patch area images of each patch area of each die of a set of identical dies on a reticle. An integrated intensity value for each patch area image is determined. A gain is applied to the integrated intensity value for each patch area image based on a pattern sparseness metric of such patch area image and its relative value to other patch area images' pattern sparseness metric. A difference between the integrated intensity value of each patch of pairs of the dies, which each pair includes a test die and a reference die, is determined to form a difference intensity map of the reticle. The difference intensity map correlates with a feature characteristic variation that depends on feature edges of the reticle. | 10-01-2015 |
Christopher Hess, Belmont, CA US
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20150270181 | OPPORTUNISTIC PLACEMENT OF IC TEST STRUCUTRES AND/OR E-BEAM TARGET PADS IN AREAS OTHERWISE USED FOR FILLER CELLS, TAP CELLS, DECAP CELLS, SCRIBE LINES, AND/OR DUMMY FILL, AS WELL AS PRODUCT IC CHIPS CONTAINING SAME - Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis. | 09-24-2015 |
Christopher Hess, San Ramon, CA US
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20080282210 | System And Method For Product Yield Prediction - A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement. | 11-13-2008 |
Christopher Hess, Larkspur, CA US
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20140201203 | SYSTEM, METHOD AND DEVICE FOR PROVIDING AN AUTOMATED ELECTRONIC RESEARCHER - A research system, method and device directed to providing a query results tree of logical dependencies in response to one or more user queries. Specifically, the research system includes a searcher module, an inference module, a front-end module and an updater module. A user query is received by the front-end module and forwarded to the searcher and inference modules, which in addition to obtaining related results from one or more databases, filter and structure the results such that only highly relevant results are returned and that those results are already organized into one or more hierarchical structures for navigation by the user. In addition, the updater module is able to periodically cause any new data on the databases to be inputted by the search and inference modules and added to the existing results in order to maintain a fully updated results structure. | 07-17-2014 |
Christopher Hess, San Carlos, CA US
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20090037131 | METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING - A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines. | 02-05-2009 |
20090140762 | LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING - A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set. | 06-04-2009 |
Christopher K. Hess, San Francisco, CA US
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20090083646 | METHOD AND SYSTEM FOR TRANSFERRING CONTENT FROM THE WEB TO MOBILE DEVICES - A web page architecture is provided for enabling a user browse the web within an inline frame embedded in a web page and drag and drop content rendered in the inline frame into a receiving panel in the web page for transmission to the user's mobile device. The delivery mechanism to receive such content on the user's mobile device may be either through SMS messaging or through communicating with a client application on the user's mobile device. | 03-26-2009 |
20100131346 | Method And System For Associating A Seller With Purchased Digital Content - An digital content management system provides a web interface for a user to purchase digital content from an online digital content store. The system is able to track the purchased digital content and deliver marketing content from the online digital content store when a user selects the purchased digital content for consumption through the web interface. | 05-27-2010 |
20100229243 | APPLICATION PROGRAMMING INTERFACE FOR TRANSFERRING CONTENT FROM THE WEB TO DEVICES - A tagging structure is used in web pages to identify content in such web pages that can be dragged and dropped into a wireless device when such web pages are rendered as a component of a web page served by a media management service. | 09-09-2010 |
20100235476 | METHOD AND SYSTEM FOR HOSTED MOBILE MANAGEMENT SERVICE ARCHITECTURE - A hosted mobile management service is provided for enabling a user to access a centralized account through a web browser on a terminal in order to manage the user's media information, such as digital music and photos. Any modifications made by user through the web browser are transparently sent to the user's mobile device where a thin client application receives such modification information and interacts with the mobile device's file system to reconcile such modifications. | 09-16-2010 |
20110153849 | METHOD AND SYSTEM FOR A HOSTED MOBILE MANAGEMENT SERVICE ARCHITECTURE - A hosted mobile management service is provided for enabling a user to access a centralized account through a web browser on a terminal in order to manage the user's media information, such as digital music and photos. Any modifications made by user through the web browser are transparently sent to the user's mobile device where a thin client application receives such modification information and interacts with the mobile device's file system to reconcile such modifications. | 06-23-2011 |
20110296315 | METHOD AND SYSTEM FOR TRANSFERRING CONTENT FROM THE WEB TO MOBILE DEVICES - A web page architecture is provided for enabling a user browse a web page and identify items of multimedia media content that the user desires to deliver to his mobile device. The delivery mechanism to transmit such content on the user's mobile device may be either through push messaging and communicating with a client application on the user's mobile device. | 12-01-2011 |
20120021733 | METHOD AND SYSTEM FOR A HOSTED MOBILE MANAGEMENT SERVICE ARCHITECTURE - A hosted mobile management service is provided for enabling a user to access a centralized account through a user interface on a terminal in order to manage the user's media information, such as digital music and photos. Any modifications made by user through the user interface are transparently sent to the user's mobile device where a module receives such modification information and interacts with the mobile device to reconcile such modifications. | 01-26-2012 |
20140165218 | Method and System for a Hosted Digital Music Library Sharing Service - A hosted web service is provided to enable the legitimate sharing and reselling digital music among subscribers to the web service by leveraging the teachings of the first sale doctrine of copyright law. By maintaining a single copy of properly purchased song within the system that can be only accessed by one subscriber at a time, the web service preserves the rights of the copyright holder of the digital music while encouraging a community sharing. | 06-12-2014 |
Duane Scott Hess, Mountain View, CA US
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20160057095 | Methods and Systems for Providing Current Email Addresses and Contact Information for Members within a Social Network - Methods and systems for providing current email addresses or contact information to members within a social network are described. In one described method, an email program application requests an email address for a member within a social network. Using profile information associated with the member, the email address is provided to the email program application which sent the request. The email address is then entered into the send-to parameter field of an email message. In another described method, contact information associated with a first member of a social can be provided to a second member of the social network. The contact information is provided if the relationship between the first and second members is an authorized relationship. The contact information associated with the first member can be used to update the contact information for the first member in an electronic address book associated with the second member. | 02-25-2016 |
Greg M. Hess, Mountain View, CA US
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20090174458 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 07-09-2009 |
20100254206 | Cache Optimizations Using Multiple Threshold Voltage Transistors - In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits. | 10-07-2010 |
20100309731 | KEEPERLESS FULLY COMPLEMENTARY STATIC SELECTION CIRCUIT - Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When a cell or data input of a given group is selected, a group select signal is provided to the global bit line circuitry. The global bit line circuitry drives a global bit line responsive to the group select signal and the data driven on (or provided to) the local bit line associated with the selected cell/input, thus providing a data output. When no cell of a given group is selected, the group select signal is de-asserted, causing the respective global bit line to be held in a predetermined state. | 12-09-2010 |
20100322026 | MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS - A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit. | 12-23-2010 |
20100329062 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 12-30-2010 |
20110032020 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 02-10-2011 |
20110235447 | LOW POWER MEMORY ARRAY COLUMN REDUNDANCY MECHANISM - A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns. | 09-29-2011 |
20110255351 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 10-20-2011 |
20120044009 | Level-Shifting Latch - A level-shifting latch circuit is disclosed. The level-shifting latch circuit may provide a level-shifting function, a data state retention function, and a dynamic-to-static conversion function. The level-shifting latch may receive two input signals from a dynamic logic circuit that are driven to the same state during a precharge phase. During an evaluation phase, one of the input signals may evaluate to a logic state complementary to the other input. The level-shifting latch circuit may generate an output signal corresponding to the input signal. On a precharge phase of a next cycle, the level-shifting latch may retain the state of the output when the two inputs are again driven to the same state. | 02-23-2012 |
20120075945 | Passgate for Dynamic Circuitry - A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the second bit line. A gate terminal of the passgate transistor may be hardwired or otherwise held to a static voltage such that it remains active when the circuit is operating. During a precharge phase, the precharge circuit may precharge the first bit line to a voltage that is at or near a supply voltage of the circuit. The second bit line may be precharged, through the passgate transistor, responsive to the precharging of the first bit line. The second bit line may be precharged to a voltage that is at least a threshold voltage less than the supply voltage. | 03-29-2012 |
20120257469 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by a control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 10-11-2012 |
20120275236 | Method and Apparatus for Power Domain Isolation during Power Down - An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain. | 11-01-2012 |
20130013862 | EFFICIENT HANDLING OF MISALIGNED LOADS AND STORES - A system and method for efficiently handling misaligned memory accesses within a processor. A processor comprises a load-store unit (LSU) with a banked data cache (d-cache) and a banked store queue. The processor generates a first address corresponding to a memory access instruction identifying a first cache line. The processor determines the memory access is misaligned which crosses over a cache line boundary. The processor generates a second address identifying a second cache line logically adjacent to the first cache line. If the instruction is a load instruction, the LSU simultaneously accesses the d-cache and store queue with the first and the second addresses. If there are two hits, the data from the two cache lines are simultaneously read out. If the access is a store instruction, the LSU separates associated write data into two subsets and simultaneously stores these subsets in separate cache lines in separate banks of the store queue. | 01-10-2013 |
20130154712 | Multiplexer with Level Shifter - A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter. | 06-20-2013 |
20130335152 | Dynamic Level Shifter Circuit and Ring Oscillator Using the Same - A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters. | 12-19-2013 |
20140112429 | Low Voltage Register File Cell Structure - A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices. | 04-24-2014 |
20140126312 | SENSE AMPLIFIER SOFT-FAIL DETECTION CIRCUIT - Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier. | 05-08-2014 |
20140129868 | SELECTABLE PHASE OR CYCLE JITTER DETECTOR - Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit. | 05-08-2014 |
20140129884 | REGISTER FILE WRITE RING OSCILLATOR - Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell. | 05-08-2014 |
20140177346 | APPARATUS TO SUPPRESS CONCURRENT READ AND WRITE WORD LINE ACCESS OF THE SAME MEMORY ELEMENT IN A MEMORY ARRAY - A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line. | 06-26-2014 |
20140177354 | ZERO KEEPER CIRCUIT WITH FULL DESIGN-FOR-TEST COVERAGE - A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input. | 06-26-2014 |
20150089250 | Contention Prevention for Sequenced Power Up of Electronic Systems - A method and apparatus for preventing contention during the sequenced power up of an electronic system is disclosed. In one embodiment, an apparatus includes first and second power domains configured to receive power from first and second power sources, respectively. During a power up sequence, the first power source is configured to provide power prior to the second power source. A power detection circuit is configured to detect the presence of power from both of the first and second power sources. If power has not been detected from the second power source, a signal provided to a clamping circuit is asserted. When the signal is asserted by the power detection circuit, the clamping circuit may inhibit the control signal received from the second power domain from being provided to a power switch in the first power domain. | 03-26-2015 |
20150348600 | CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE - A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits. | 12-03-2015 |
20160062388 | SELECTABLE PHASE OR CYCLE JITTER DETECTOR - Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit. | 03-03-2016 |
20160071574 | METHOD AND CIRCUITS FOR LOW LATENCY INITIALIZATION OF STATIC RANDOM ACCESS MEMORY - A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously. | 03-10-2016 |
Greg M. Hess, Mounntain View, CA US
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20110255355 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 10-20-2011 |
Harry Fuku Hess, Hermosa Beach, CA US
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20120151915 | JOINT FOR HOUSING ALIGNMENT - An assembly kit includes a first turbocharger component flange with receptacles spaced according to a first interval angle; a second turbocharger component flange with receptacles spaced according to a second interval angle that differs from the first interval angle; and a piece configured for receipt by a receptacle of the first component and a receptacle of the second component where alignment of the receptacles determines a rotational orientation angle of the first component with respect to the second component. Various other examples of devices, assemblies, systems, methods, etc., are also disclosed. | 06-21-2012 |
Jeff Hess, Coto De Caza, CA US
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20120296572 | SYSTEM AND METHOD FOR REAL-TIME SAMPLE ANALYSIS - A system for predicting the amount of VOCs in an extruded product includes a container holding a gaseous sample, a detector in communication with the container for analyzing the gaseous sample, and a processor in communication with the detector and programmed to analyze the data from the detector and predict the amount of VOCs in an extruded product. A method of predicting an amount of extractable volatile organic compounds in an extruded product includes delivering a sample of gas from an intermediate stage in an extrusion process to a detector, analyzing the sample of gas using the detector to obtain data about the amount of VOCs in the sample of gas, delivering the data to a processor, comparing the data to control data to generate comparison data, and predicting the amount of extractable VOCs in the extruded product. | 11-22-2012 |
Jeff Hess, San Diego, CA US
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20150029264 | MULTI-COLOR PRINTER WITH INK PLUMBING FOR OPTIMIZED NOZZLE HYDRATION - A multi-color printer has an array of monochrome fixed inkjet printheads aligned in a media feed direction. The printer includes: a first printhead positioned furthest upstream relative to the media feed direction; a second printhead positioned furthest downstream relative to the media feed direction; and a third printhead positioned between the first and second printheads. Each printhead is supplied with a respective ink from a multi-color ink set, the first printhead being supplied with a lowest luminance ink of the ink set and the third printhead being supplied with a highest luminance ink of the ink set. | 01-29-2015 |
Jonathan J. Hess, Los Altos, CA US
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20140025684 | INDEXING AND SEARCHING A DATA COLLECTION - A system searches a data collection using a bloom filter index to reduce the search scope to improve search efficiency, while at the same time allowing more flexible searches of the data collection using search terms containing any arbitrary string of data. | 01-23-2014 |
20140123039 | Auto Localization - Exemplary methods, apparatuses, and systems receive a preferred language and a base file that includes localizable and non-localizable user interface objects, the text string associated with the localizable user interface objects, and the respective ID codes of the user interface objects. Substitute the text string of localizable user interface objects in the base file with the text string in a localization text file referenced by the ID code. Generate a user interface window with the user interface objects including the text from the localization text file. | 05-01-2014 |
Jonathan Joseph Hess, Los Altos, CA US
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20150347097 | ADAPTIVE USER INTERFACES - Systems, methods, and computer-readable storage media for creating and displaying adaptive user interfaces are disclosed. An example method includes receiving a user interface by an application development environment, the application development environment providing the ability to allow authoring of a user interface that adapts to a screen size with any first abstracted size class value and any second abstracted size class value. The method then includes creating an application including the user interface wherein the application is configured to: determine a screen size of a device, the screen size including a first abstracted size class value and a second abstracted size class value; adapt the user interface according to the screen size including the first abstracted size class value and the second abstracted size class value; and display the adapted user interface on the device. | 12-03-2015 |
Kenneth Lee Hess, Anaheim Hills, CA US
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20110237051 | PROCESS AND APPARATUS FOR DEPOSITION OF MULTICOMPONENT SEMICONDUCTOR LAYERS - A deposition process involves the formation of multicomponent semiconductor layers, in particular III-V epitaxial layers, on a substrate. Due to pyrolytic decomposition inside the reaction chamber, one of the process gases forms a first decomposition product. Together with a second decomposition product of a second process gas, the decomposition products form a layer on the surface of a heated substrate and also adhere to surfaces of the process chamber. To remove these adherences, during an etching step a purge gas containing a reactive substance formed by free radicals is introduced into the process chamber. The etching step may be performed before or after the deposition process. | 09-29-2011 |
Martin L. Hess, Aptos, CA US
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20090113347 | INFORMATION PRESENTATION AND MANAGEMENT IN AN ONLINE TRADING ENVIRONMENT - A method includes receiving, from a user, publication data to be published and location data identifying a storage location at which an image to be associated with the publication data is stored. The image to be included in the publication data is retrieved from the storage location identified by the location data. A reduced-size image using the retrieved image is generated and the reduced-size image is aggregated with further reduced-size images for presentation at a remote site. | 04-30-2009 |
20090192919 | PERIODICALLY RELOADING IMAGE IN ORDER TO OBTAIN ANY CHANGES TO THE IMAGES - A method of managing images between computers over a network. The method includes receiving a first product description and a first image location of the first product, the first image location referencing a first storage computer on the network; receiving a second product description and a second image location of the second product, the second image location referencing a second storage computer on the network; retrieving the first image from the first storage computer based on the first image location; producing a first thumbnail image from the first image; retrieving the second image from second first storage computer based on the second image location; producing a second thumbnail image from the second image; periodically reloading the first image and the second image in order to obtain any changes that were made to the first image and the second image; and updating the first thumbnail image and the second thumbnail image. | 07-30-2009 |
20110229050 | AGGREGATION OF REDUCED-SIZED IMAGES - A method includes receiving, from a first user, first location data identifying a first storage location at which a first image is stored, The first image is retrieved from the first storage location identified by the first location. A first reduced-size image is generated using the first image. The first reduced-size image is aggregated with a second reduced-size image for presentation at a remote site, the second reduced-size image being generated using a second image retrieved from a second storage location identified by second location data received from a second user. | 09-22-2011 |
Narada Hess, Menlo Park, CA US
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20110038479 | DEVELOPING INITIAL AND SUBSEQUENT KEYID INFORMATION FROM A UNIQUE MEDIAID VALUE - A technique for using a key repository to store data encryption keys provides a way to access key records in the key repository using a key identifier constructed from a media identifier associated with a data storage medium on which encrypted data is or will be stored. The media identifier is hashed and added to a counter value to produce the key identifier. In some embodiments, the technique is implemented in an encryption switch that provides data-at-rest encryption for a storage access network, but in other embodiments, the technique may be implemented in other devices, including data storage devices and hosts. | 02-17-2011 |
Narada Jared Hess, Menlo Park, CA US
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20110038482 | Scalable Key Archival - A solution for scalable key archival includes, at a network device, determining whether a key management device that is not part of a current key management device configuration has been newly added to a network. The method also includes, if the key management device has been newly added to the network, determining whether the network device has a first application program interface (API) or device driver for communicating with the key management device. The method also includes, if the network device does not have the first API, obtaining the API. The method also includes creating a binding between a virtual device driver of the network device and the key management device via the first API, the network device having a second API for communications between the virtual device driver and a security processor of the network device. The security processor communicates with the key management device using the second API. | 02-17-2011 |
Phillip B. Hess, Los Angeles, CA US
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20110053546 | OPTIMAL NARROWBAND INTERFERENCE REMOVAL FOR SIGNALS SEPARATED IN TIME - A system and method for improving the processing of communications signals received in the presence of narrowband interference signals. The received communications signals are time sampled and transformed into a series of spectral terms in the frequency domain that are then evaluated to identify narrowband interference signals. The identified narrowband interference terms can be calculated to a value that will optimize the corrupted spectral terms resulting from the communication, and an inverse transformation can be used to generate a time domain signal that is free from interference. | 03-03-2011 |
Randy Hess, Turlock, CA US
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20090223948 | MAGNETIC WATER HEATER - A heater includes a first rotor rotatably mounted to a support structure, and a first magnet attached to the first rotor. A second rotor is rotatably mounted to the support structure to be substantially coaxial with the first rotor, and a second magnet is attached to the second rotor. A tank that is at least partially formed from an electrically conductive material is disposed between the first rotor and the second rotor. A drive mechanism is configured to rotate the first rotor in a first direction and the second rotor in a second direction opposite the first direction. | 09-10-2009 |
Ron Hess, Monte Sereno, CA US
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20080209503 | METHOD AND SYSTEM FOR MANAGING LICENSE OBJECTS TO APPLICATIONS IN AN APPLICATION PLATFORM - Systems and methods are provided for managing license objects to applications in an application platform database system. The method includes associating an LMA with an application installed to the application platform by a developer, notifying a license manager to which the license manager application is installed of the installation of the application to the application platform, and managing subscriber access to the application using the license manager application. | 08-28-2008 |
20110197287 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EVALUATING METADATA BEFORE EXECUTING A SOFTWARE APPLICATION - Systems and methods are provided for managing license objects to applications in an application platform database system. The method includes associating an LMA with an application installed to the application platform by a developer, notifying a license manager to which the license manager application is installed of the installation of the application to the application platform, and managing subscriber access to the application using the license manager application. | 08-11-2011 |
Ronald Vance Hess, Monte Sereno, CA US
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20100070323 | Method and system for wealth management - In accordance with embodiments, there are provided mechanisms and methods for wealth management. These mechanisms and methods for wealth management can enable embodiments to provide a multi-tenant database that stores information about clients of the tenants. In a multi-tenant database, a system for managing financial accounts is established, which may be useful for a tenant that is a financial analyst or that employs financial analysts. The multi-tenant database may include a calendar application that automatically includes the team members associated with the event being scheduled in a list of invitees, and the multi-tenant database may also includes relationship groups, such that information about related individuals (whom may have separate accounts) are automatically associated with one another. The ability of embodiments that provide relationship groups and teams can enable efficiently gathering information about related parties and efficiently inviting that interested parties to an event. | 03-18-2010 |
20110213797 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR SHARING A SINGLE INSTANCE OF A DATABASE STORED USING A TENANT OF A MULTI-TENANT ON-DEMAND DATABASE SYSTEM - In accordance with embodiments, there are provided mechanisms and methods for sharing a single instance of a database stored using a tenant of a multi-tenant on-demand database system. These mechanisms and methods for sharing a single instance of a database stored using a tenant of a multi-tenant on-demand database system can provide a single instance of a database that is shared amongst tenants of a multi-tenant on-demand database system. The ability to provide a single instance of a database that is shared amongst tenants of a multi-tenant on-demand database system can enable the database to be managed or otherwise maintained in a central location. | 09-01-2011 |
20140188939 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR SHARING A SINGLE INSTANCE OF A DATABASE STORED USING A TENANT OF A MULTI-TENANT ON-DEMAND DATABASE SYSTEM - In accordance with embodiments, there are provided mechanisms and methods for sharing a single instance of a database stored using a tenant of a multi-tenant on-demand database system. These mechanisms and methods for sharing a single instance of a database stored using a tenant of a multi-tenant on-demand database system can provide a single instance of a database that is shared amongst tenants of a multi-tenant on-demand database system. The ability to provide a single instance of a database that is shared amongst tenants of a multi-tenant on-demand database system can enable the database to be managed or otherwise maintained in a central location. | 07-03-2014 |
Ruwen Henning Hess, Long Beach, CA US
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20120233496 | FAULT TOLERANCE IN A PARALLEL DATABASE SYSTEM - Embodiments are directed to establishing a fault tolerant parallel database system and to detecting the health of parallel database services. In an embodiment, a computer system establishes a control node cluster that includes at least one active control node and at least one spare control node. Each node of the control node cluster includes specific functions assumable only by other control nodes. The computer system also establishes a compute node cluster that includes at least one active computing node, at least one spare computing node, at least one active storage node and at least one spare storage node. Each of the computing and storage nodes includes specific functions assumable only by other computing and storage nodes. The computer system detects a failure of an active node and instantiates a corresponding spare node that is configured to perform the functions of the failed active node. | 09-13-2012 |
Sean Hess, Los Angeles, CA US
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20150023509 | APPARATUS AND METHOD FOR PERFORMING AN AUDIO MEASUREMENT SWEEP - In at least one embodiment, an apparatus for performing an audio measurement is provided. The apparatus includes a controller that is programmed to generate an audio test signal based on a first frequency range that comprises a first noise spectrum, a second frequency range that comprises a second noise spectrum, and a third frequency range that comprises a third noise spectrum and to transmit the audio test signal to an audio device that generates an audio response signal responsive to the audio test signal. The controller is further programmed to receive the audio response signal and to determine audio related characteristics for the audio device in response to the audio response signal. | 01-22-2015 |
Sonja Hess, Arcadia, CA US
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20080203303 | SINGLE ELECTRODE CORONA DISCHARGE ELECTROCHEMICAL/ELECTROSPRAY IONIZATION - A single electrode electrochemical/electrospray ionization source using a corona discharge and a method of analyzing a sample using a corona discharge single electrode electrochemical/electrospray ionization source are provided. In the corona discharge single electrode electrochemical/electrospray ionization technique electrons are removed from the metal tip of the device through gases present in the electrospray ion source resulting in electrochemical ionization of the sample of interest. The resulting odd electron sample cation (positive ion mode) or anion (negative ion mode) can then be analyzed by an appropriate technique, such as, for example, a mass spectrometer. | 08-28-2008 |