Patent application number | Description | Published |
20090054918 | Thrombectomy System and Method - Disclosed is a clot and foreign body removal system, including a catheter with at least one lumen. Located within the catheter is a clot capture wire that is connected to a hub at the proximal end. In one embodiment, the clot capture wire includes a coil made out of an elastic or superelastic material, preferably nitinol. The elasticity or superelasticity of the coil allows it to be deformed within the catheter and to then reform its original coil configuration when the coil is moved outside of the catheter lumen. In another embodiment the coil is a biphasic, shape memory coil, which changes shape upon heating, energy application, or passing an electric current. Once the coil configuration has been established, the coil can be used to ensnare and corkscrew a clot or blockage in a vessel. A clot is extracted from the vessel by moving the clot capture coil and catheter proximally until the clot can be removed completely or released into a different vessel that does not perfuse a critical organ. Foreign bodies are similarly captured by deploying the coil distal to the foreign body and moving the clot capture coil proximally until the foreign body is trapped within the coil. By removing the device from the body, the foreign material is also removed. | 02-26-2009 |
20090082809 | System and Method for Minimally Invasive Posterior Fixation - The present invention relates generally to systems and methods for aligning and implanting orthopedic fixation or stabilization implants within the body. In one embodiment, the system includes at least two bone anchors, at least one of which is provided with an angularly adjustable connector. In one aspect, the system also includes at least one linkage rod, for linking two or more bone anchors through their respective adjustable connectors. The bone anchors and the linkage rod may be locked into place to form a spinal fusion or fixation prosthesis. An alignment tool is provided, for guiding a guidewire through one or more connectors. | 03-26-2009 |
20110257741 | IMPLANTS AND METHODS FOR RESHAPING HEART VALVES - Tissue shaping methods and devices are provided for reinforcing and/or remodeling heart valves. In certain embodiments, magnetic tissue shaping devices are implanted in tissue adjacent heart valve leaflets. The devices are mutually attractive or repulsive so as to remodel the heart tissue and improve heart valve function. In certain other embodiments, one or more tissue shaping devices including shape memory material are implanted in a patient's body within or on tissue adjacent a heart valve leaflet. The shape memory material can be activated within the patient in a less invasive or non-invasive manner, such as by applying energy percutaneously or external to the patient's body. The shape memory tissue shaping devices are implanted in a first configuration and then activated to remember a second configuration that displaces tissue so as to remodel the heart valve geometry and improve heart valve function. In certain other embodiments, a brace is crimped to the base of a heart valve leaflet to support the leaflet and improve valve closure. | 10-20-2011 |
20110264132 | MULTI-UTILITARIAN MICROCATHETER SYSTEM AND METHOD OF USE - A device for performing therapeutic or diagnostic procedures within the cerebrovasculature includes a catheter having a distal portion, a proximal portion and a lumen extending therebetween, the catheter including an expandable region for engaging the vessel wall, thrombus, atheroma, or other structures. The device further includes an elongate stretching member, which can be a guidewire, insertable longitudinally through the lumen of the catheter, the elongate stretching member being configured for stretching at least a portion of the catheter and causing the expandable region to transition from an expanded state to a collapsed state, and wherein the elongate stretching member is retracted proximally relative to the catheter causes the expandable region to transition from the radially collapsed state to a radially, or laterally expanded state. | 10-27-2011 |
20130035726 | SYSTEM AND METHOD FOR MINIMALLY INVASIVE POSTERIOR FIXATION - The present invention relates generally to systems and methods for aligning and implanting orthopedic fixation or stabilization implants within the body. In one embodiment, the system includes at least two bone anchors, at least one of which is provided with an angularly adjustable connector. In one aspect, the system also includes at least one linkage rod, for linking two or more bone anchors through their respective adjustable connectors. The bone anchors and the linkage rod may be locked into place to form a spinal fusion or fixation prosthesis. An alignment tool is provided, for guiding a guidewire through one or more connectors. | 02-07-2013 |
Patent application number | Description | Published |
20110163373 | Semiconductor device including a voltage controlled termination structure and method for fabricating same - According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device. | 07-07-2011 |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |
20120211825 | Trench MOSFET and Method for Fabricating Same - According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. | 08-23-2012 |
20130264636 | Trench FET with Ruggedness Enhancement Regions - According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches. | 10-10-2013 |
20140118032 | Buck Converter Power Package - One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip. | 05-01-2014 |
20140332879 | Power Semiconductor Device with Reduced On-Resistance and Increased Breakdown Voltage - In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device. | 11-13-2014 |
20140339651 | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness. | 11-20-2014 |
20140339669 | Semiconductor Device with a Field Plate Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric. | 11-20-2014 |
20140339670 | Semiconductor Device with a Thick Bottom Field Plate Trench Having a Single Dielectric and Angled Sidewalls - Disclosed is a power device, such as a power MOSFET device and a method for fabricating same. The device includes a field plate trench. The field plate trench has a predetermined width and a predetermined sidewall angle. The device further includes a single trench dielectric on sidewalls of the field plate trench and at a bottom of the field plate trench. The single trench dielectric has a bottom thickness that is greater than a sidewall thickness. The device also includes a field plate situated within the single trench dielectric. | 11-20-2014 |
20140374825 | Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches - Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another. | 12-25-2014 |
Patent application number | Description | Published |
20150279946 | Power Semiconductor Device with Embedded Field Electrodes - A power semiconductor device is disclosed. The power semiconductor device includes an upper drift region situated over a lower drift region, a field electrode embedded in the lower drift region, the field electrode not being directly aligned with a gate trench in a body region of the power semiconductor device, where respective top surfaces of the field electrode and the lower drift region are substantially co-planar. A conductive filler in the field electrode can be substantially uniformly doped, and the field electrode is in direct electrical contact with the upper drift region. | 10-01-2015 |
20150325685 | Power Semiconductor Device with Low RDSON and High Breakdown Voltage - A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench. | 11-12-2015 |
20160104766 | Power Semiconductor Device with Source Trench and Termination Trench Implants - A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench. | 04-14-2016 |
20160104773 | Semiconductor Structure Having Integrated Snubber Resistance and Related Method - A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions. | 04-14-2016 |
Patent application number | Description | Published |
20110137740 | PROCESSING VALUE-ASCERTAINABLE ITEMS - Techniques are provided for allowing a merchant to process third party closed-loop instruments (such as gift cards) as if the closed-loop instruments were open-loop instruments. A customer provides card data of a third party gift card to a merchant, e.g., online or in a merchant store, for the purchase of one or more items provided by the merchant. The merchant sends the gift card data to an intermediary that deducts at least a portion of the balance of the gift card. The intermediary sends an offer for the gift card to the customer. If the customer accepts the offer, then the merchant applies the offer towards the total purchase price of the one or more items. | 06-09-2011 |
20120059736 | PROCESSING VALUE-ASCERTAINABLE ITEMS - Techniques are provided for allowing a merchant to process third party closed-loop instruments (such as gift cards) as if the closed-loop instruments were open-loop instruments. A customer provides card data of a third party gift card to a merchant, e.g., online or in a merchant store, for the purchase of one or more items provided by the merchant. The merchant sends the gift card data to an intermediary that deducts at least a portion of the balance of the gift card. The intermediary sends an offer for the gift card to the customer. If the customer accepts the offer, then the merchant applies the offer towards the total purchase price of the one or more items. | 03-08-2012 |
20120143705 | PROCESSING VALUE-ASCERTAINABLE ITEMS - Techniques are provided for allowing a merchant to process third party closed-loop instruments (such as gift cards) as if the closed-loop instruments were open-loop instruments. A customer provides card data of a third party gift card to a merchant, e.g., online or in a merchant store, for the purchase of one or more items provided by the merchant. The merchant sends the gift card data to an intermediary that deducts at least a portion of the balance of the gift card. The intermediary sends an offer for the gift card to the customer. If the customer accepts the offer, then the merchant applies the offer towards the total purchase price of the one or more items. | 06-07-2012 |
20120221405 | PROCESSING VALUE-ASCERTAINABLE ITEMS - Techniques are provided for allowing a merchant to process third party closed-loop instruments (such as gift cards) as if the closed-loop instruments were open-loop instruments. A customer provides card data of a third party gift card to a merchant, e.g., online or in a merchant store, for the purchase of one or more items provided by the merchant. The merchant sends the gift card data to an intermediary that deducts at least a portion of the balance of the gift card. The intermediary sends an offer for the gift card to the customer. If the customer accepts the offer, then the merchant applies the offer towards the total purchase price of the one or more items. | 08-30-2012 |
20120221425 | PROCESSING VALUE-ASCERTAINABLE ITEMS - Techniques are provided for allowing a merchant to process third party closed-loop instruments (such as gift cards) as if the closed-loop instruments were open-loop instruments. A customer provides card data of a third party gift card to a merchant, e.g., online or in a merchant store, for the purchase of one or more items provided by the merchant. The merchant sends the gift card data to an intermediary that deducts at least a portion of the balance of the gift card. The intermediary sends an offer for the gift card to the customer. If the customer accepts the offer, then the merchant applies the offer towards the total purchase price of the one or more items. | 08-30-2012 |