Patent application number | Description | Published |
20080246056 | SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET - Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel. | 10-09-2008 |
20090029531 | HYBRID ORIENTATION SUBSTRATE AND METHOD FOR FABRICATION THEREOF - A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate. | 01-29-2009 |
20090146181 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS - An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer. | 06-11-2009 |
20090242989 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR - In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction. | 10-01-2009 |
20100009502 | Semiconductor Fabrication Process Including An SiGe Rework Method - A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C. | 01-14-2010 |
20100059764 | STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS - A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions. | 03-11-2010 |
20110237039 | Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions - Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein. | 09-29-2011 |
20110318897 | Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor - Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants. | 12-29-2011 |
20120119307 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 05-17-2012 |
20120129312 | METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS - Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse. | 05-24-2012 |
20130149830 | METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING SILICON-GERMANIUM SOURCE/DRAIN REGIONS THEREIN - Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions. | 06-13-2013 |
20130178053 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 07-11-2013 |
20140099763 | FORMING SILICON-CARBON EMBEDDED SOURCE/DRAIN JUNCTIONS WITH HIGH SUBSTITUTIONAL CARBON LEVEL - Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement. | 04-10-2014 |
20140191297 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 07-10-2014 |
20140252413 | SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin. | 09-11-2014 |
20140252479 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 09-11-2014 |
20140353741 | BOTTLED EPITAXY IN SOURCE AND DRAIN REGIONS OF FETS - A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions. | 12-04-2014 |
20140377924 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 12-25-2014 |
20150014773 | Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 01-15-2015 |
20150021625 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 01-22-2015 |