Patent application number | Description | Published |
20100121628 | INTEGRATED CIRCUIT VERIFICATION DEVICE AND METHOD - An integrated circuit verification device includes a trace-back unit having structure data of an integrated circuit to be verified, and configured to trace back nodes of the integrated circuit in a direction from an output node to an input node; and a state defining unit having data with respect to a target state of the output node of the integrated circuit, and configured to sequentially define states of back-traced nodes to satisfy the target state of the output node. | 05-13-2010 |
20110158033 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively. | 06-30-2011 |
20110270599 | METHOD FOR TESTING INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file representing the signal waveforms by detecting a waveform change of the signals, and analyzing the text file. | 11-03-2011 |
20130163364 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via. | 06-27-2013 |
20130166944 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell array comprising a normal memory cell and a redundancy memory cell and configured to store data, a data compression unit configured to compress data stored in the memory cell array and generate compression information, and a repair control unit configured to control a repair operation for accessing the redundancy memory cell in response to the compression information. | 06-27-2013 |
20140063977 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal. | 03-06-2014 |
20140355364 | MEMORY AND MEMORY SYSTEM - A memory may include first to N | 12-04-2014 |
20150198653 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system includes a semiconductor chip; a penetrating electrode, which is formed to penetrate the semiconductor chip; two or more metals, which are formed in the upper portion of the penetrating electrode; a bump, which is formed to contact the upper portions of the metals and supplies a data signal inputted from outside to the metals; a detection block suitable for detecting whether or not the bump is coupled with the metals by comparing voltage levels of the metals with each other and generating a decision signal; and a signal output block suitable for outputting the decision signal externally. | 07-16-2015 |