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He, TX

Chen He, Austin, TX US

Patent application numberDescriptionPublished
20110078521TRANSITION FAULT TESTING FOR A VON-VOLATILE MEMORY - A method is for testing a non-volatile memory. A base data pattern is defined for a first pageset of the non-volatile memory. The non-volatile memory has a plurality of pages which comprise words. The base pattern is arranged so that each bitpair of a plurality of bitpairs that includes one of a group consisting of even bitpairs and odd bitpairs formed from all of the words exhibits all possible bitpair transitions during sequential accesses of the pages of the plurality of pages. The base pattern is stored in the first pageset. The pages of the plurality of pages of the first pageset are accessed sequentially.03-31-2011
20120014179SOFT PROGRAM OF A NON-VOLATILE MEMORY BLOCK - A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.01-19-2012
20120072794NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION - A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.03-22-2012
20120113714METHOD FOR PROGRAMMING A MULTI-STATE NON-VOLATILE MEMORY (NVM) - A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.05-10-2012
20120117307NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE - A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.05-10-2012
20120131262Method and Apparatus for EEPROM Emulation for Preventing Data Loss in the Event of a Flash Block Failure - A defect resistant EEPROM emulator (05-24-2012
20120201082ERASE RAMP PULSE WIDTH CONTROL FOR NON-VOLATILE MEMORY - A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.08-09-2012
20120206973Digital Method to Obtain the I-V Curves of NVM Bitcells - A calibration table (08-16-2012
20120327710ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY - A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A level of the voltage is compared to a reference. If the level of the voltage is below the reference, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.12-27-2012
20120327720ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY USING VERIFY READ - A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A determination is made if the voltage insufficient for performing the write operation on the memory cells of the memory array. If a level of the voltage is insufficient, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells. The reduced number of memory cells is a first subset of the memory cells.12-27-2012
20130107621BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT05-02-2013
20130194874Dynamic Healing Of Non-Volatile Memory Cells - Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.08-01-2013
20130238831METHOD FOR IMPLEMENTING SECURITY OF NON-VOLATILE MEMORY - An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.09-12-2013
20130290797NON-VOLATILE MEMORY (NVM) RESET SEQUENCE WITH BUILT-IN READ CHECK - A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.10-31-2013
20130290808ERASING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.10-31-2013
20130308402TEST FLOW TO DETECT A LATENT LEAKY BIT OF A NON-VOLATILE MEMORY - A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.11-21-2013
20130326285STRESS-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A NON-VOLATILE MEMORY ARRAY - A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.12-05-2013
20140029351METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR PROGRAM/ERASE OPERATIONS TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations.01-30-2014
20140040687Non-Volatile Memory (NVM) with Imminent Error Prediction - A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.02-06-2014
20140078829NON-VOLATILE MEMORY (NVM) WITH ADAPTIVE WRITE OPERATIONS - A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate.03-20-2014
20140098615LATENT SLOW BIT DETECTION FOR NON-VOLATILE MEMORY - In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.04-10-2014
20140136928PROGRAMMING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.05-15-2014
20140160869BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT - A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.06-12-2014
20140204678DYNAMIC DETECTION METHOD FOR LATENT SLOW-TO-ERASE BIT FOR HIGH PERFORMANCE AND HIGH RELIABILITY FLASH MEMORY - A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.07-24-2014
20140254285Temperature-Based Adaptive Erase or Program Parallelism - A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.09-11-2014
20140269111NON-VOLATILE MEMORY (NVM) WITH BLOCK-SIZE-AWARE PROGRAM/ERASE - A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of the selected block; determining a set of program/erase voltages based on the array size and temperature from a temperature sensor; and programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block.09-18-2014
20150023106Adaptive Erase Recovery For Non-Volatile Memory (NVM) Systems - Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.01-22-2015
20150049555Extended Protection For Embedded Erase Of Non-Volatile Memory Cells - Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (V02-19-2015
20150085593NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT - A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.03-26-2015
20150117112ADAPTIVE ERASE METHODS FOR NON-VOLATILE MEMORY - A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.04-30-2015

Patent applications by Chen He, Austin, TX US

Chen He, Cedar Park, TX US

Patent application numberDescriptionPublished
20090168541ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING - A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable.07-02-2009

Haiping He, Spring, TX US

Patent application numberDescriptionPublished
20110209771Liquid Impact Pressure Control Methods and Systems - The present invention discloses apparatuses, systems, and methods for controlling liquid impact pressure in liquid impact systems. The liquid impact systems include at least one gas and a liquid, the gas having a density (PG) and a polytropic index (κ) and the liquid having a density (PL). The methods include the step of calculating a liquid impact load of the liquid on the object by determining a parameter Ψ for the system, wherein Ψ is defined as (PG/PL) (κ−1)/κ. The systems are also configured to utilize the parameter Ψ. The parameter Ψ may be adjusted to increase or reduce the liquid impact load on the system. Automatic, computer-implemented systems and methods may be used or implemented. These methods and systems may be useful in applications such as LNG shipping and loading/off-loading, fuel tank operation, manufacturing processes, vehicles dynamics, and combustion processes, among others.09-01-2011

Jia He, College Station, TX US

Patent application numberDescriptionPublished
20140124205PROCESS TO FRACTURE A SUBTERRANEAN FORMATION USING A CHELATING AGENT - The present invention relates to a process for fracturing a subterranean formation comprising a step of fracturing the formation and a step of introducing a treatment fluid containing glutamic acid N,N-diacetic acid or a salt thereof (GLDA), methylglycine N,N-diacetic acid or a salt thereof (MGDA) and/or N-hydroxyethyl ethylenediamine N,N′,N′-triacetic acid or a salt thereof (HEDTA) into the formation, wherein the fracturing step can take place before introducing the treatment fluid into the formation, while introducing the treatment fluid into the formation or subsequent to introducing the treatment fluid into the formation.05-08-2014

Jian He, Sugar Land, TX US

Patent application numberDescriptionPublished
20150034315VISCOSIFIED ACID FLUID AND METHOD FOR USE THEREOF - A method includes providing an oilfield treatment fluid including an aqueous HCl solution having greater than 15% HCl by weight, and a fixing agent (FA) in a molar ratio of FA:HCl of between 0.5 and 2.5 inclusive. The FA is urea and/or a urea derivative. The oilfield treatment fluid further includes a viscosifying agent that is not a plant-based polysaccharide gum. The method further includes providing the oilfield treatment fluid to a high pressure pump, and operating the high pressure pump to treat a formation fluidly coupled to a wellbore.02-05-2015
20150034318AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - A method of treating a formation includes preparing an aqueous solution having HCl in an amount between greater than 15% and 45.7% by weight, inclusive. The prepared aqueous solution includes a fixing agent (FA) present in a molar ratio of FA:HCl between 0.15 and 2.5 inclusive, where the FA is urea and/or a urea derivative, and further includes water present in an amount sufficient to dissolve the HCl and the FA. The aqueous solution includes substantially no polysaccharides.02-05-2015
20150037234AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - An aqueous solution includes HCl present in an amount exceeding 37% by weight. The solution further includes a fixing agent that is urea and/or a urea derivative. The fixing agent is present in the solution in a molar ratio of between 0.25 and 2.0 of fixing agent to HCl, inclusive.02-05-2015
20150114647AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Aqueous compositions contain hydrochloric acid at a concentration between 8 wt % and 28 wt % inclusive. The amino acid; hydrochloric acid mole ratio may be between 0.2 and 1.5. Sufficient water is present to dissolve the hydrochloric acid and the amino acid. Such compositions have utility as retarders for acid compositions employed in the stimulation of subterranean formations. Slowing the reaction between the acid and formation helps maximize formation permeability and productivity.04-30-2015
20150122485AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Oilfield treatment compositions contain water, hydrochloric acid at a concentration between 15 wt % and 45.7 wt % and a first and second fixing agent. The first fixing agent comprises urea, a urea derivative or both. The second fixing agent may be a mixture or amines and alcohols. These compositions provide corrosion inhibition when exposed to steel. The compositions may also contain an inhibitor aid.05-07-2015
20150122499AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Oilfield treatment compositions contain water, hydrochloric acid at a concentration between 15 wt % and 45.7 wt % and a first fixing agent. The first fixing agent comprises urea, a urea derivative or both. The molar ratio between the first fixing agent and water may be higher than or equal to 0.5, and urea is the dominant solvent species in the compositions. In these compositions the first fixing agent provides corrosion inhibition when exposed to steel. The compositions may also contain a second fixing agent and an inhibitor aid.05-07-2015
20150240147AQUEOUS SOLUTION AND METHODS FOR MANUFACTURE AND USE - Oilfield treatment compositions contain water, hydrochloric acid and urea. The urea and water may be present at a urea/water weight ratio between 0.8 and 12.0, and the hydrochloric acid and urea may be present at a urea/hydrochloric acid molar ratio between 0.1 and 0.5. The compositions are present as one liquid phase. The volumes of the compositions are substantially higher than those of the water volumes; consequently, the amount of water necessary to perform various well-service operations is lower.08-27-2015

Jianli He, Houston, TX US

Patent application numberDescriptionPublished
20100252824Hybrid Molecular Electronic Devices Containing Molecule-Functionalized Surfaces for Switching, Memory, and Sensor Applications and Methods for Fabricating Same - This invention is generally related to a method of making a molecule-surface interface comprising at least one surface comprising at least one material and at least one organic group wherein the organic group is adjoined to the surface and the method comprises contacting at least one organic group precursor with at least one surface wherein the organic group precursor is capable of reacting with the surface in a manner sufficient to adjoin the organic group and the surface. The present invention is directed to hybrid molecular electronic devices having a molecule-surface interface. Such hybrid molecular electronic devices may advantageously have either a top or bottom gate electrode for modifying a conductivity of the devices.10-07-2010

Jie He, Austin, TX US

Patent application numberDescriptionPublished
20160078529SYSTEM AND METHOD FOR MAPPING AND MONITORING DEPOSIT CHANNELS - In order to prevent false positives at a duplicate transaction detection system, channel deposit data from financial institutions (representing the manner of presentment of checks at those institutions) are provided to a channel mapping/monitoring system. The channel mapping monitoring system calculates a prediction interval representing a normal expected range of deposits in any given channel. If deposits at a financial institution fall outside the normal expected range, the channel mapping/monitoring system provides an alert to the financial institution.03-17-2016

Jie He, Houston, TX US

Patent application numberDescriptionPublished
20140050777Liposomal Formulations of Polymyxin and Uses Thereof - The present invention provides novel liposomal formulations of polymyxin B and pharmaceutical compositions thereof useful for the treatment of bacterial infections. The liposomal formulation comprises a lipid component formed as vesicles each having a minimum size of at least 500 nm and polymyxin B encapsulated in the vesicles. The present invention also provides a drug delivery system that comprises a plurality of liposomes encapsulating a polymyxin B therein, where the liposomes have a minimum vesicular size of at least 500 nm. The liposomes comprising the drug delivery system are useful to increase efficacy of a treatment for a bacterial infection by increasing bioavailability and distribution of the polymyxin B within the subject.02-20-2014

Jin He, Plano, TX US

Patent application numberDescriptionPublished
20120112723Loosely Regulated Feedback Control for High Efficiency Isolated DC-DC Converters - The improved DC-DC converter apparatus includes a primary side circuit and a secondary side circuit that is galvanically isolated from the primary. The primary side induces a voltage in the secondary side that provides an output voltage for driving POLs. A controller in the primary senses a reflected output voltage signal that is coupled from the secondary and is proportional to the secondary output voltage with respect to a voltage regulation point determined by either a voltage divider circuit or the zener voltage in the secondary. The voltage regulation point is established by wide-tolerance electrical components, such as a zener diode, a resistor, or a combination, connected in the coupling device circuit.05-10-2012
20130050954Thermal Management System and Method - A thermal management system/method allowing efficient electrical/thermal attachment of heat sourcing PCBs to heat sinking PCBs using reflow/wave/hand soldering is disclosed. The disclosed system/method may incorporate a combination of support pins, spacer pads, and/or contact paste that mechanically attaches a heat sourcing PCB (and its associated components) to a heat sinking PCB such that thermal conductivity between the two PCBs can be optimized while simultaneously allowing controlled electrical conductivity between the two PCBs. Controlled electrical isolation between the two PCBs is provided for using spacer pads that may also be thermal conductive. Contact paste incorporated in some embodiments permits enhanced conductivity paths between the heat sourcing PCB, a thermally conductive plate mounted over the heat sourcing PCB, and the heat sinking PCB. The use of self-centering support pins incorporating out-gassing vents in some embodiments allows reflow/wave/hand soldering as desired.02-28-2013
20130335043MULTI-LEVEL VOLTAGE REGULATOR SYSTEM AND METHOD - A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.12-19-2013
20150319886Thermal Management System and Method - A thermal management system/method allowing efficient electrical/thermal attachment of heat sourcing PCBs to heat sinking PCBs using reflow/wave/hand soldering is disclosed. The disclosed system/method may incorporate a combination of support pins, spacer pads, and/or contact paste that mechanically attaches a heat sourcing PCB (and its associated components) to a heat sinking PCB such that thermal conductivity between the two PCBs can be optimized while simultaneously allowing controlled electrical conductivity between the two PCBs. Controlled electrical isolation between the two PCBs is provided for using spacer pads that may also be thermally conductive. Contact paste incorporated in some embodiments permits enhanced conductivity paths between the heat sourcing PCB, a thermally conductive plate mounted over the heat sourcing PCB, and the heat sinking PCB. The use of self-centering support pins incorporating out-gassing vents in some embodiments allows reflow/wave/hand soldering as desired.11-05-2015

Patent applications by Jin He, Plano, TX US

Jin He, Dallas, TX US

Patent application numberDescriptionPublished
20120164071Compositions and Methods Comprising Phosphatidylethanolamine-Binding Peptide Derivatives - Disclosed are surprising discoveries concerning the role of anionic phospholipids and aminophospholipids in tumor vasculature and in viral entry and spread, and compositions and methods for utilizing these findings in the treatment of cancer and viral infections. Also disclosed are advantageous antibody, immunoconjugate and duramycin-based compositions and combinations that bind and inhibit anionic phospholipids and aminophospholipids, for use in the safe and effective treatment of cancer, viral infections and related diseases.06-28-2012

Ji Wei He, Arlington, TX US

Patent application numberDescriptionPublished
20090157141WIRELESS NEURAL RECORDING AND STIMULATING SYSTEM - Apparatus and methods are provided for the management of neural activity in an individual. Nerve activity is sensed and correlated with sensations such as pain. In response and without requiring input from the individual, although external input is contemplated, a signal is transmitted to another component for electrical stimulation that alters neural activity. Also, the modulation of the signals between the sensor and stimulator may be modified by a third component independently, independent of, or including user inputs.06-18-2009

Kai He, Kingwood, TX US

Patent application numberDescriptionPublished
20160083639MULTI-FUNCTIONAL SURFACTANT COMPLEXES FOR USE IN SUBTERRANEAN FORMATIONS - Systems and methods for creating and/or using multi-functional surfactant complexes that may enhance surfactant treatments in subterranean formations are provided. In some embodiments, the methods comprise: providing a treatment fluid comprising an aqueous base fluid and one or more multi-functional surfactant complexes that comprise at least one surfactant and at least one polymeric additive, wherein the surfactant and the polymeric additive carry opposite charges; and introducing the treatment fluid into a well bore at a well site penetrating at least a portion of a subterranean formation.03-24-2016

Ku He, Austin, TX US

Patent application numberDescriptionPublished
20150303932COMPARATOR TRACKING CONTROL SCHEME WITH DYNAMIC WINDOW LENGTH - A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.10-22-2015
20150381130REDUCING AUDIO ARTIFACTS IN A SYSTEM FOR ENHANCING DYNAMIC RANGE OF AUDIO SIGNAL PATH - In accordance with embodiments of the present disclosure, an apparatus for providing an output signal to an audio transducer may include a control circuit. The control circuit may be configured to predict, based on a magnitude of a signal indicative of the output signal, an occurrence of an event for changing a selectable digital gain and a selectable analog gain and an audio signal path, and responsive to predicting the occurrence of the event, change, at an approximate time in which a zero crossing of the signal indicative of the output signal occurs, the selectable digital gain and the selectable analog gain.12-31-2015
20160072465SYSTEMS AND METHODS FOR GAIN CALIBRATION OF AN AUDIO SIGNAL PATH - A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error.03-10-2016
20160080862SYSTEMS AND METHODS FOR REDUCTION OF AUDIO ARTIFACTS IN AN AUDIO SYSTEM WITH DYNAMIC RANGE ENHANCEMENT - In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.03-17-2016
20160080865SYSTEMS AND METHODS FOR REDUCTION OF AUDIO ARTIFACTS IN AN AUDIO SYSTEM WITH DYNAMIC RANGE ENHANCEMENT - In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.03-17-2016

Ming He, Houston, TX US

Patent application numberDescriptionPublished
20090037759Clock shifting and prioritization system and method - A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device.02-05-2009
20110151811Wireless Device With Selectable Antennas - Systems and methods for improving antenna performance and reducing antenna volume are disclosed herein. In one embodiment, a wireless communication device includes a first antenna, a second antenna, and a radio frequency receiver. The first antenna is tuned to support a first set of radio frequency bands. The second antenna is tuned to support a second set of radio frequency bands. The radio frequency receiver combines signals detected by the first and second antennas to produce a baseband signal. The second set of radio frequency bands is different from the first set of radio frequency bands.06-23-2011

Patent applications by Ming He, Houston, TX US

Perry P. He, Austin, TX US

Patent application numberDescriptionPublished
20080205633Estimating delay of an echo path in a communication system - Methods and corresponding systems for reducing an echo signal include assigning a subsegment delay to each of a plurality of subsegment adaptive filters. A send signal and a delayed receive signal are coupled to each of the subsegment adaptive filters, wherein the delayed receive signal is delayed according to a respective subsegment delay. A set of filter coefficients in each of the subsegment adaptive filters are adapted, in parallel, to correspond to a respective subsegment impulse response of a connected system. Each set of filter coefficients is analyzed to produce a pure delay, and the pure delay is used to delay the receive signal for a main adaptive filter. An echo signal replica is produced using the main adaptive filter and an error signal. The echo signal replica is subtracted from the send signal to produce the error signal.08-28-2008

Patent applications by Perry P. He, Austin, TX US

Qingyan He, Pearland, TX US

Patent application numberDescriptionPublished
20090025924Sensor and Insulation Layer Structure for Well Logging Instruments - A logging sonde includes a tube defining a sealed chamber inside. An isolation layer is disposed on an exterior of the tube. At least one sensor is disposed on an exterior of the isolation layer. The sensor includes a lead in passing through a wall of the tube. An elastomer jacket is disposed on an exterior of the sensor and the isolation layer. A method for making a sonde includes affixing an electrically insulating isolator to an exterior of a tube. An hydraulic seal layer is affixed over an exterior of the isolator. A sensor is affixed over the exterior of the seal layer. An electrical connection is made from the sensor to an interior of the tube through the hydraulic seal layer and through the isolator. An elastomer jacket is applied over the exterior of at least part of the sensor and the exterior of the seal layer.01-29-2009
20090072832Transducer Assemblies for Subsurface Use - Transducer apparatus for subsurface use. A tubular configured for subsurface disposal is equipped with a cylindrical transducer module formed of a non-conductive material. The module is mounted to surround a section of the tubular and includes a transducer element disposed thereon such that only a surface of the element is exposed along the exterior of the module body. The transducer element is linked to a lead routed through the cylindrical body to exit near the inner bore of the body. The ends of the cylindrical body are covered with a material to form a hydraulic seal. A method for constructing the transducer apparatus.03-19-2009
20100180662COMPOSITE MATERIALS AND CALIBRATION ASSEMBLIES USING THE SAME - Example composite materials and calibration assemblies using the same. An example calibration assembly for use in calibrating a downhole formation evaluation tool includes a first body comprising a first material and having a first geometry, a second body comprising a second material formed to receive the first body, wherein the first and second materials and the first geometry are selected so that a calibration property of the calibration assembly substantially matches a corresponding calibration property of a third material.07-22-2010
20130091922Composite Materials And Calibration Assemblies Using The Same - A calibration assembly is disclosed. In one embodiment, a calibration assembly calibrating a downhole formation evaluation tool includes a calibration base having a first geometry, a calibration insert including a first material and having a second geometry, and a second material having a third geometry and being different from the first material. The second geometry enables the calibration insert to receive the second material to form a first composite region, wherein the first and second materials and the second and third geometries are selected such that a calibration property of the calibration assembly apparatus substantially matches a corresponding calibration property of a third material. Additional apparatuses, devices, and methods are also disclosed.04-18-2013

Patent applications by Qingyan He, Pearland, TX US

Ran He, Houston, TX US

Patent application numberDescriptionPublished
20150270465NbFeSb-Based Half-Heusler Thermoelectric Materials and Methods of Fabrication and Use - A thermoelectric half-Heusler material comprising niobium (Nb), iron (Fe) and antimony (Sb) wherein the material comprises grains having a mean grain size less than one micron. A method of making a nanocomposite half-Heusler thermoelectric material includes melting constituent elements of the thermoelectric material to form an alloy of the thermoelectric material, comminuting (e.g., ball milling) the alloy of the thermoelectric material into nanometer scale mean size particles, and consolidating the nanometer size particles to form the half-Heusler thermoelectric material comprising at least niobium (Nb), iron (Fe) and antimony (Sb) and having grains with a mean grain size less than one micron.09-24-2015

Robert He, Pflugerville, TX US

Patent application numberDescriptionPublished
20150332033TWO OR THREE STEP AUTHORIZATION VIA TAPPING - Example methods and systems directed to a Transaction Manager are described. According to various embodiments, the Transaction Manager generates modules and sends modules to various computing devices. The modules, when executed on a computing device(s), cause a computing device(s) to execute various actions described below. Transaction Manager sends modules to a wireless mobile device. Upon executing the modules, the wireless mobile device receives a transaction initiation message and presents an alert upon receipt of the transaction initiation message. The wireless mobile device detects an occurrence of a physical gesture and recognizes the occurrence of the physical gesture as authorization to proceed with a transaction. The wireless mobile device sends a response to the transaction initiation message based on detecting the occurrence of the physical gesture. The response includes a customer identification for the transaction. The customer identification is associated with an account through which the transaction can be fulfilled.11-19-2015
20150333960PHONE THERMAL CONTEXT - A method and a system a thermal context manager (hereinafter “TCM”) detects a thermal state and a position of a computing device. Based on the detected thermal state(s) and the detected position(s) of the computing device, the TCM initiates an action associated with the computing device. The TCM continually monitors the computing device in order to create a thermal state profile of the computing device. To create the thermal state profile, the TCM stores data representing each detected instance of the thermal state of the computing device and data representing each detected position of the computing device.11-19-2015
20160048892LOCATION AND TIME-BASED CONVERSATIONS FOR DISCUSSING RELEVANT INFORMATION - A system, method, and computer readable medium is provided to identify a user that can provide relevant information to another user currently located at a particular location. A device location (DL) manager receives first data indicating a presence of a first computing device at a location that corresponds to an item. The first computing device is associated with a first user account. The DL manager sends a first notification to the first user account due to activity related to the item by a second user account. The first notification identifies the second user account. The DL manager receives a message from the first user account for the second user account.02-18-2016
20160069705METHODS AND SYSTEMS FOR DETERMINING ROUTING - Systems and methods are presented for sequencing locations and events and determining routing and itineraries for the sequence. In some embodiments the system may receive a starting location, a first location, and a second location in a default order. The system may determine a sequence from the starting location for the first location and the second location. The system may generate a route for the sequence with the route having transportation directions between the starting location, the second location, and the first location indicative of the sequence. The system may display the route in a graphical user interface of an application.03-10-2016

Robert He, Austin, TX US

Patent application numberDescriptionPublished
20150355893SYSTEMS AND METHODS FOR LOCATION-BASED APPLICATION INSTALLATION - A system and/or method may be provided to install applications based on location. In particular, a location of a user device may be detected. Based on the location of the user device, one or more applications may be selected to be installed automatically on the user device. Further, when the user device departs from the location, the application may automatically be uninstalled. Thus, applications may be installed and/or uninstalled on the user device based on the location of the user device. The automatically installed application may provide functionality or information associated with the location that triggered the installation. For example, a merchant's store may be associated with the merchant's application which may be installed automatically on devices of customers who enter the merchant's store.12-10-2015

Ruo-Hua He, Dallas, TX US

Patent application numberDescriptionPublished
20150063753ENHANCED COUPLING STRENGTH GRATINGS - The present invention includes an optical waveguide with a grating and a method of making the same for increasing the effectiveness of the grating. In one example, the grating is at least partially covered by a liner layer disposed on at least a portion of a grating; and a cover layer disposed on the liner layer, wherein a first material selected for the core and ridges and a second material selected for the liner layer are selected to provide a difference in the index of refraction between the first and second material that is sufficient to provide a contrast therebetween.03-05-2015

Ting He, Austin, TX US

Patent application numberDescriptionPublished
20130002668SYSTEMS AND METHODS FOR DISPLAYING, VIEWING AND NAVIGATING THREE DIMENSIONAL REPRESENTATIONS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a three dimensional (3D) representation, where the multiple objects are visual representations of real objects, and display a subset of the objects and associated metadata in a shaped lens that is movable within the 3D representation in all three axes, where the subset of the objects displayed within the shaped lens are sized larger than the objects outside of the shaped lens.01-03-2013
20130002723SYSTEMS AND METHODS FOR DISPLAYING AND VIEWING DATA MODELS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a single pane, where the multiple objects are visual representations of real objects and the multiple objects are dynamically sized and spaced relative to one another to fit all of the objects in the single pane. The computer program product includes executable code that, when executed, causes the data processing apparatus to display a subset of the objects and associated metadata in an examination frame. The examination frame is sized to fit within the single pane, where the subset of the objects displayed within the examination frame are sized larger than the objects outside of the examination frame.01-03-2013
20130086507DISPLAY WINDOW WITH MULTI-LAYER, PARALLEL TAB DISPLAY - A layer manager provides at least two content layers within a user interface window of a software application. A tab manager provides at least two content tabs within at least one of the content layers. A transfer manager is configured to transfer at least one content tab between the at least two content layers.04-04-2013
20140111520USER-CENTRIC ANNOTATED LOCATION AWARE ASSET MAPPING - According to one general aspect, a method may include receiving a floor map indicating the structural layout of a predefined physical location. The method may also include receiving a point-of-interest (POI) data structure representing a POI and POI metadata associated with the POI. The method may include generating an annotated floor map, based upon the floor map and including a POI indicator, wherein the POI indicator is placed on the floor map at the location of an associated POI and indicates both the type of the associated POI and at least part of the status of the associated POI. The method may include displaying, via a display interface, at least a portion of the annotated floor map.04-24-2014
20140113559PROACTIVE ROLE AWARE ASSET MONITORING - According to one general aspect, a method may include establishing a short-range wireless communication between a user device and a point-of-interest (POI) device, wherein the POI device is associated with a POI data structure that represents a physical POI. The method may include receiving a request to perform a POI action in regards to the physical POI. The method may include causing the POI action to be performed.04-24-2014
20140114931MANAGEMENT OF ANNOTATED LOCATION AWARE ASSETS - According to one general aspect, a method may include storing, in a memory device, a plurality of floor maps, each floor map indicating the structural layout of a respective predefined physical location. The method may include storing, in a memory device, a plurality of point-of-interest (POI) data structures. Each POI data structure may include a physical location of an associated POI. The method may include receiving a floor map request from a client computing device, wherein the floor map request includes a requested location. The method may include based upon the location included by the floor map request, selecting a selected floor map and a selected subset of the plurality of POI data structures. The method may include transmitting, to the client computing device, a response to the floor map request based upon the selected floor map and the selected POI data structures.04-24-2014
20140365121USER-CENTRIC ANNOTATED LOCATION AWARE ASSET MAPPING - According to one general aspect, a method may include receiving a floor map indicating a structural layout of a physical location, receiving a point-of-interest (POI) data structure representing a POI and POI metadata associated with the POI, POI data structure including a location of an associated POI that is associated with the POI, and the POI metadata including a POI type indicating a type of the associated POI, and a POI status indicating the status of the associated POI, annotating the floor map by overlaying on the selected floor map an indicator for each selected POI data structure such that the indicator is placed on the floor map at a location representing the physical location of the respective associated POI and indicates the type of the associated POI and the status of the associated POI, displaying a portion of the annotated floor map, and initiating a POI action.12-11-2014
20140365489MANAGEMENT OF ANNOTATED LOCATION AWARE ASSETS - A method may include storing a plurality of floor maps, each floor map indicating a structural layout of a respective physical location, storing a plurality of point-of-interest (POI) data structures, each POI data structure including a physical location of an associated POI that is associated with the respective POI data structure, receiving a floor map request, the floor map request including a requested location, based upon the location included by the floor map request, selecting a floor map and a subset of the plurality of POI data structures, for each of the subset of the plurality of POI data structures, receiving metadata from the associated POI, the metadata indicating a status of the associated POI, and transmitting, to the client computing device and in response to the floor map request, the selected floor map and the selected POI data structures.12-11-2014
20150161806SYSTEMS AND METHODS FOR DISPLAYING AND VIEWING DATA MODELS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a single pane, where the multiple objects are visual representations of real objects and the multiple objects are dynamically sized and spaced relative to one another to fit all of the objects in the single pane. The computer program product includes executable code that, when executed, causes the data processing apparatus to display a subset of the objects and associated metadata in an examination frame. The examination frame is sized to fit within the single pane, where the subset of the objects displayed within the examination frame are sized larger than the objects outside of the examination frame.06-11-2015
20160078012SYSTEMS AND METHODS FOR FORMLESS INFORMATION TECHNOLOGY AND SOCIAL SUPPORT MECHANICS - A system includes a user interface having a text input box configured to receive input from a user, the input including text and/or an action indicator, and a response area for displaying results and/or action selection buttons in response to the input from the text input box. The system includes an application engine that receives the input from the text input box as a user types each character into the text input box, performs a search and present results to the search in the response area, in response to receiving additional text input from the text input box, performs the search and presents updated results to the search in the response area, and in response to receiving text and an action indicator from the text input box, causes an action corresponding to the action indicator to be performed and causes a change to the user interface corresponding to the action.03-17-2016

Patent applications by Ting He, Austin, TX US

Weigong He, Sugar Land, TX US

Patent application numberDescriptionPublished
20110189670Circulating Tumor and Tumor Stem Cell Detection Using Genomic Specific Probes - The present invention comprises a method of detecting circular tumor cells and methods of detecting, evaluating, or staging cancer in a patient, as well as a method of monitoring treatment of cancer in a patient using the claimed method. The method comprises contacting a sample with a CD45 binding agent; selecting the cells based on positive or negative CD45 staining; contacting the selected cells with a labeled nucleic acid probe, and detecting hybridized cells by fluorescence in situ hybridization; and analyzing a signal produced by the labels on the hybridized cells to detect the CTCs. In other embodiments, the method provides for directed to a method of determining the level of CTCs in a sample having blood cells from a patient by contacting a sample having blood cells from a patient, wherein the sample has not been pre-sorted into CD45-positive and CD45-negative cells.08-04-2011
20140256597Method of amplifying and labeling the mRNA sample for mRNA microarray - Disclosed is method of amplifying and labeling mRNA sample for the mRNA microarray. The invention utilizes the specific synthesized single strand oligonucleotide (ssDNA) poly-T to hybridize the complementary poly-A in the tail of the mRNA; converts the hybridized mRNA to the cDNA; hybridizes the mRNA detection probe on the mRNA microarray chip with the cDNA; amplifies the hybridized cDNA through extending the polymer based on the ssDNA; labels the amplified cDNA by integrating the fluorescent modified nucleotide into the amplified duplex oligonucleotide during polymer extension; verifies the amplified labeled cDNA through detecting the fluorescent signal. The fluorescent signal from the mRNA detection probe spot on the mRNA microarray chip will indicate the presence of the detected mRNA and the quantity of the fluorescent signal from the mRNA detection probe sport will be directly proportional to the amount of the fluorescent modified nucleotide in the amplified duplex oligonucleotide.09-11-2014

Weiguo He, Pearland, TX US

Patent application numberDescriptionPublished
20140100120METHODS OF X-APTAMER GENERATION AND COMPOSITIONS THEREOF - Provided herein are methods for a novel bead-based next-generation “X-aptamer” selection scheme that extends aptamer technology to include X-modified bases, thus resulting in X-aptamers, at any position along the sequence because the aptamers are chemically synthesized via a split-pool scheme on individual beads. Also provides are application to a wide range of commonly used DNA modifications, including, but not limited to, monothioate and dithioate backbone substitutions. This new class of aptamer allows chemical modifications introduced to any of the bases in the aptamer sequence as well as the phosphate backbones and can be extended to other carbohydrate-based systems.04-10-2014

Xiaojie He, Austin, TX US

Patent application numberDescriptionPublished
20090239468WIRELESS MASS STORAGE FLASH MEMORY - Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless communication technology to another based on signal strength, signal quality, the distance between the memory module and a host component, power usage, as well as other criteria to facilitate an optimal data transmission or throughput rate.09-24-2009

Patent applications by Xiaojie He, Austin, TX US

Xihua He, San Antonio, TX US

Patent application numberDescriptionPublished
20150211103HYDRIDING OF METALLIC SUBSTRATES - The present disclosure relates to a method for accelerated hydriding of metallic substrates to evaluate the effects of hydrogen adsorption on substrate performance. The method includes applying to the substrate a metal that has an activation energy for hydrogen adsorption that is lower than the substrate activation energy for hydrogen adsorption. This is then followed by hydriding and evaluation of the effects of hydriding on substrate mechanical properties.07-30-2015

Yan He, Plano, TX US

Patent application numberDescriptionPublished
20140267035Multimodal User Interface Design - A multimodal user interface is provided. A human machine interface in a vehicle utilizes a plurality of modalities. A cognitive model for secondary driving tasks indicates a best use of one or more particular modalities for performing each secondary driving task.09-18-2014

Yingzi He, Austin, TX US

Patent application numberDescriptionPublished
20150304426METHOD OF MANAGING AN APPLICATION IN A SECURE ELEMENT - The invention is a method of managing an application embedded in a secure element which is able to communicate with another device through a HTTP session. The application has previously registered for being triggered when a preset event will occur into the secure element. The triggering of the application is blocked as a HTTP session is in progress between the secure element and the device when the preset event occurs.10-22-2015

Zhaohui He, Austin, TX US

Patent application numberDescriptionPublished
20100327765LOW ENERGY TRANSFER MODE FOR AUXILIARY POWER SUPPLY OPERATION IN A CASCADED SWITCHING POWER CONVERTER - A cascaded power converter having an auxiliary power supply operated from the second switching power stage provides efficient operation by activating the auxiliary power supply early in the startup process. A low energy transfer operating mode is initiated in the second switching power stage to charge the auxiliary power supply output without generating significant disruption at the load. After the first switching power stage is started and the intermediate node voltage has increased to a level sufficient to operate the second switching power stage, the final switching power stage enters a normal operating mode. The low energy transfer operating mode has a substantially reduced switching rate and pulse width from that of the normal operating mode.12-30-2010
20120153858Switching Parameter Based Discontinuous Mode-Critical Conduction Mode Transition - An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage.06-21-2012
20120306406CONTROL DATA DETERMINATION FROM PRIMARY-SIDE SENSING OF A SECONDARY-SIDE VOLTAGE IN A SWITCHING POWER CONVERTER - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the controller determines the one or more switching power converter control parameters using a resonant period factor from a reflected secondary-side voltage and an occurrence of an approximate zero voltage crossing of the secondary-side voltage during a resonant period of the secondary-side voltage. In at least one embodiment, the switching power converter control parameters include (i) an estimated time of a minimum value of the secondary-side voltage during the resonant period and (ii) an estimated time at which a current in the secondary-side of the transformer decayed to approximately zero.12-06-2012
20120306407Primary-Side Control Of A Switching Power Converter With Feed Forward Delay Compensation - An electronic system includes controller to control a switching power converter to provide power to a load. To control the amount of power provided to the load, in at least one embodiment, the controller senses a current value representing a current in the switching power converter and detects when the current value reaches a target peak value. However, due to delays in the controller and/or the switching power converter, the detected target peak value will not be the actual current peak value generated by the switching power converter. In at least one embodiment, the controller adjusts the detected target peak value with a post-detection delay compensation factor to generate a delay compensated current value that more accurately represents an actual peak current value associated with the current in the switching power converter.12-06-2012
20130002163Input Voltage Sensing For A Switching Power Converter And A Triac-Based Dimmer - An electronic lighting system and method described herein control energy provided to an electronic lighting device, such as one or more light-emitting diodes (LEDs) and/or compact fluorescent lamps (CELs), of the electronic lighting system. A triac-based dimmer phase cuts a line voltage provided to the electronic lighting system. A controller of the electronic lighting system utilizes a probing system to overcome idiosyncrasies of the triac-based dimmer to allow the controller to probe and sense the line voltage. To reduce energy consumption, rather than probing each cycle of the output voltage of the triac-based dimmer, the controller periodically or intermittently probes the output voltage of the triac-based dimmer.01-03-2013
20130154495Adaptive Current Control Timing and Responsive Current Control for Interfacing with a Dimmer - In at least one embodiment, an electronic system adapts current control timing for half line cycle of a phase-cut input voltage and responsively controls a dimmer current in a power converter system. The adaptive current control time and responsive current control provides, for example, interfacing with a dimmer. The electronic system and method include a dimmer, a switching power converter, and a controller to control the switching power converter and controls a dimmer current. In at least one embodiment, the controller determines a predicted time period from a zero crossing until a leading edge of a phase-cut input voltage and then responsively controls the dimmer current to, for example, reduce current and voltage perturbations (referred to as “ringing”), improve efficiency, and reduce an average amount of power handled by various circuit components.06-20-2013
20130154496MULTI-MODE FLYBACK CONTROL FOR A SWITCHING POWER CONVERTER - In at least one embodiment, an electronic system and method includes a controller to control a switching power converter in at least two different modes of operation depending on whether the controller detects a dimmer or not and/or whether a load requests more power than either of the two operational modes can provide. In at least one embodiment, the controller detects whether a dimmer is phase cutting an input voltage to a switching power converter. The controller operates the switching power converter in a first mode if the dimmer is detected, and the controller operates the switching power converter in a second mode if the dimmer is not detected. The controller also transitions between operating the switching power converter in the first mode and the second mode if a status of detection of the dimmer changes.06-20-2013
20140028095ACCELERATION OF OUTPUT ENERGY PROVISION FOR A LOAD DURING START-UP OF A SWITCHING POWER CONVERTER - An electronic system and method include a controller to operate in a start-up mode to accelerate driving a load to an operating voltage and then operates in a post-start-up mode. A start-up condition occurs when the controller detects that a load voltage is below a predetermined voltage threshold level. The predetermined voltage threshold level is set so that the controller will boost the voltage to an operating value of a load voltage at a faster rate than during normal, steady-state operation. The controller causes a switching power converter to provide charge to the load at a rate in accordance with a start-up mode until reaching an energy-indicating threshold. When the energy-indicating threshold has been reached, the controller causes the switching power converter to (i) decrease the amount of charge provided to the load relative to the charge provided during the start-up mode and (ii) operate in a distinct post-start-up-mode.01-30-2014
20140028213ACTIVE THERMAL PROTECTION FOR SWITCHES - A system and method include a controller that reduces power dissipated by a switch, such as a source-controlled field effect transistor, when an estimated amount of power dissipated by the switch exceeds a predetermined threshold. Reducing the power dissipated by the switch prevents damage to the switch due to overheating. The controller determines the estimated amount of power dissipated by the switch using actual drain-to-source current and drain voltage data. In at least one embodiment, the controller includes a fail-safe, estimated power dissipation determination path that activates when the drain voltage data fails a reliability test. Additionally, in at least one embodiment, the controller includes a model of thermal characteristics of the switch. In at least one embodiment, the controller utilizes real-time estimated power dissipation by the switch and the model to determine when the estimated power dissipated by the switch exceeds a power dissipation protection threshold.01-30-2014
20140252981Utilizing Secondary-Side Conduction Time Parameters of a Switching Power Converter to Provide Energy to a Load - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the switching power converter utilizes a transformer to transfer energy from a primary-side of the transformer to a secondary-side of the transformer. In at least one embodiment, the switching power converter control parameters includes a secondary-side conduction time delay that represents a time delay between when the primary-side ceases conducting a primary-side current and the secondary-side begins to conduct a secondary-side current. In at least one embodiment, determining and accounting for this secondary-side conduction time delay increases the prediction accuracy of the secondary-side current value and accurate delivery of energy to a load when the controller does not directly sense the secondary-side current provided to the load.09-11-2014
20140252990Quantization Error Reduction in Constant Output Current Control Drivers - An electronic system and method includes a controller to control a switching power converter in at least two different modes of operation, a normal mode and an error reduction mode. The controller controls an amount of charge pushed (i.e. delivered) by the switching power converter to a load to reduce a charge quantization error. The charge quantization error represents an amount of charge pushed to the load beyond a target charge amount. The controller determines an amount of charge to be pushed to the toad. Based on the amount of charge to be pushed to the load, the controller generates a current control signal that controls a current control switch in the switching power converter. Determination of the control signal depends on whether the controller is operating in normal mode or error reduction mode. The controller attempts to reduce the charge quantization error to avoid power fluctuations.09-11-2014
20150340955Switching Parameter Based Discontinuous Mode-Critical Conduction Mode Transition - An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage.11-26-2015
20150340956Utilizing Secondary-Side Conduction Time Parameters of a Switching Power Converter to Provide Energy to a Load - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the switching power converter utilizes a transformer to transfer energy from a primary-side of the transformer to a secondary-side of the transformer. In at least one embodiment, the switching power converter control parameters includes a secondary-side conduction time delay that represents a time delay between when the primary-side ceases conducting a primary-side current and the secondary-side begins to conduct a secondary-side current. In at least one embodiment, determining and accounting for this secondary-side conduction time delay increases the prediction accuracy of the secondary-side current value and accurate delivery of energy to a load when the controller does not directly sense the secondary-side current provided to the load.11-26-2015
20150351178Adaptive Current Control Timing and Responsive Current Control for Interfacing with a Dimmer - In at least one embodiment, an electronic system adapts current control timing for half line cycle of a phase-cut input voltage and responsively controls a dimmer current in a power converter system. The adaptive current control time and responsive current control provides, for example, interfacing with a dimmer. The electronic system and method include a dimmer, a switching power converter, and a controller to control the switching power converter and controls a dimmer current. In at least one embodiment, the controller determines a predicted time period from a zero crossing until a leading edge of a phase-cut input voltage and then responsively controls the dimmer current to, for example, reduce current and voltage perturbations (referred to as “ringing”), improve efficiency, and reduce an average amount of power handled by various circuit components.12-03-2015

Patent applications by Zhaohui He, Austin, TX US

Zhe Y. He, Cypress, TX US

Patent application numberDescriptionPublished
20140367115MULTI POWER LAUNCH SYSTEM FOR PRESSURE DIFFERENTIAL DEVICE - An injection mandrel may include a valve controlling the flow of the injection fluid. A valve actuator operatively connected to the valve sequentially generates a first predetermined pressure and a larger second predetermined pressure in the valve. The valve actuator generates the second predetermined pressure in the valve in response to a predetermined change in a pressure at an annulus surrounding the mandrel.12-18-2014

Zhi Y. He, Cypress, TX US

Patent application numberDescriptionPublished
20160040503PRESSURE DIFFERENTIAL DEVICE - In one aspect, a pressure differential device including: an inlet; an outlet; and a fluid restricting member fluidly associated with the inlet and the outlet, wherein the fluid restricting member is configured to provide a first backpressure at a first setting and a second plurality of backpressures at a plurality of second settings. In another aspect, a method to control backpressure including: providing a fluid line with an inlet fluid flow; supplying the inlet fluid flow into a pressure differential device; expelling an outlet fluid flow out of the pressure differential device; pressurizing the inlet fluid flow to a first backpressure at a first setting of the pressure differential device; pressurizing the inlet fluid flow to a second plurality of backpressures at a plurality of second settings of the pressure differential device.02-11-2016

Zhi Yong He, Cypress, TX US

Patent application numberDescriptionPublished
20130056216Dynamic Self-Cleaning Downhole Debris Reducer - A debris reducer for reducing debris within a fluid flow line having a lower screen that is secured within the flow line, the lower screen having a lower screen cage with a lower cutting portion. A debris reducer element is retained within the flow line and is moveably disposed with respect to the lower screen. The debris reducer element has an upper screen cage with an upper cutting portion. The upper and lower screen cages overlap and move the upper and lower cutting portions with respect to each other to reduce debris within fluid flowing through the flow line.03-07-2013
20130180592Valve for Use in Chemical Injectors and the Like - A valve having an outer housing defining a central bore with a fluid inlet and a fluid outlet. A check dart assembly, valve seat and piston assembly are retained within the central bore. The valve is moveable between open and closed positions in response to fluid flow into the fluid inlet of the valve.07-18-2013
20150144352CHEMICAL INJECTION MANDREL PRESSURE SHUT OFF DEVICE - Disclosed herein is a shut off system for a hydrocarbon recovery mandrel comprising an inline valve assembly comprising a nipple comprising a chemical flow line; the chemical flow line being operative to transfer fluids from outside the wellbore to a mandrel channel; where the mandrel channel is disposed in the mandrel; a valve assembly comprising a cylinder and a piston shaft; where the cylinder contacts the chemical flow line; where the piston shaft reciprocates in the cylinder in response to opposing applied pressures; where the piston shaft contacts a sealing object that is operative to facilitate or to prevent fluid flow from the chemical flow line to the mandrel channel; where the cylinder comprises a port that provides fluid communication from the cylinder to the mandrel channel; and an actuating assembly; where the actuating assembly is operative to displace the piston shaft in the cylinder to prevent fluid communication between the chemical flow line and the mandrel channel.05-28-2015
20150144353DOWNHOLE SYSTEM HAVING CHEMICAL INJECTION VALVE ASSEMBLY AND METHOD OF CHEMICAL INJECTION - A downhole system having a chemical injection valve assembly configured to inject at least one chemical from a chemical injection line into a downhole tubing. The chemical injection valve assembly includes a passive access control mechanism configured to reveal a first port to the tubing in a first condition and block the first port in a second condition. The passive access control mechanism including a movable piston, wherein in the first condition the piston is exposed to a first pressure source on a first side of the piston. To a second pressure source on a second side of the piston and the first pressure source from within the tubing and the second pressure source from outside of the chemical injection line and the tubing. Also included is a method of chemical injection in a downhole system.05-28-2015
20160053577PRESSURE DIFFERENTIAL DEVICE WITH CONSTANT PRESSURE DROP - In one aspect, an apparatus for use in a wellbore is disclosed, including: an inlet; an outlet; and a variable flow restriction configured to provide a predetermined constant pressure drop between the inlet and the outlet in response to a range of inlet flow rates. In another aspect, a method for providing a fluid flow within a wellbore is disclosed, including: providing the fluid flow to an inlet; restricting the fluid flow to provide a predetermined constant pressure drop between the inlet and an outlet in response to a range of fluid flow rates; and providing the fluid flow to the wellbore from the outlet.02-25-2016
20160084390MULTISTAGE FLOW CONTROL DEVICE AND METHOD OF CONTROLLING FLOW OF FLUID THROUGH A TUBULAR - A multistage flow control device includes, a tubular with a plurality of one or more openings, a plurality of seats positioned at the tubular, and a plurality of plugs that are movable relative to the tubular between at least a first position sealingly engaged with one of the plurality of seats and a second position displaced from the one of the plurality of seats. Each of the plurality of plugs is movable from the first position to the second position in response to a pressure differential applied thereacross achieving a threshold value with a first of the plurality of plugs moving at a first threshold value and a second of the plurality of plugs moving at a second threshold value.03-24-2016

Patent applications by Zhi Yong He, Cypress, TX US

Zhongli He, Austin, TX US

Patent application numberDescriptionPublished
20080240252SIMPLIFIED DEBLOCK FILTERING FOR REDUCED MEMORY ACCESS AND COMPUTATIONAL COMPLEXITY - A method of simplifying deblock filtering of video blocks of an enhanced layer of scalable video information is disclosed which includes selecting an adjacent pair of video blocks, determining whether boundary strength of the video blocks is a first value, evaluating first conditions using component values of a first component line if the boundary strength is not the first value, and bypassing deblock filtering between the video blocks if the boundary strength is the first value or if any of the first conditions is false. The method may include bypassing evaluating conditions and deblock filtering associated with the maximum boundary strength. The method may include bypassing evaluating second conditions and bypassing corresponding deblock filtering if the intermediate edge is a horizontal edge. The method may include bypassing less efficient memory reads associated with component values used for evaluating the second conditions.10-02-2008
20090060035TEMPORAL SCALABILITY FOR LOW DELAY SCALABLE VIDEO CODING - A method of processing video information which includes receiving encoded video information including an encoded base layer frame and encoded enhanced layer frames for providing temporal scalability, decoding the encoded video information in display order, and using a decoded first enhanced layer frame as a reference frame for decoding a second enhanced layer frame for forward prediction. Processing the video information in display order and using a decoded enhanced layer frame as a reference frame for processing another enhanced layer frame for forward prediction reduces coding latency for achieving temporal scalability for low delay scalable video coding. The coding memory space may also be reduced as compared to bidirectional prediction coding since the number of reference frames used for coding may be reduced.03-05-2009
20100260269VIDEO DECODING WITH ERROR DETECTION AND CONCEALMENT - A system and method of decoding input video information is disclosed which includes performing error detection for each video block of a frame, determining whether a scene change occurs for the frame, and when an error is detected in a video block, performing spatial concealment by concealing error of the erroneous video block using neighboring video information within the frame when the erroneous video block is intraframe encoded or when a scene change is detected for the frame, or performing temporal concealment by replacing the erroneous video block with a reference video block from a reference frame when the erroneous video block is interframe encoded and when a scene change is not detected for the frame. The method may further include detecting false frames based on comparing current and new frame number and picture order count values of a new slice.10-14-2010
20110032430DYNAMIC COMPENSATION OF DISPLAY BACKLIGHT BY ADAPTIVELY ADJUSTING A SCALING FACTOR BASED ON MOTION - A video adjustment system for processing video information is disclosed which includes a motion analyzer and an adjustment module. The motion analyzer determines a motion level metric of the video information based on at least one motion parameter. The adjustment adjusts an initial dynamic light scaling factor to provide an adjusted dynamic light scaling factor based on the motion level. The dynamic light scaling factor may be used for luminance compensation and backlight display scaling. The motion level may be based on any type of motion information, such as motion vector information or information indicating a scene change. A distortion module may perform a distortion evaluation of the video information for calculating the initial scaling factor. Alternatively, the distortion module may include a memory which stores predetermined scaling factors based on statistical distortion level characterization.02-10-2011
20110116539METHOD AND APPARATUS FOR VIDEO DECODING WITH REDUCED COMPLEXITY INVERSE TRANSFORM - A method of reducing processing of fast inverse transform of an input transform block by a video decoder includes determining whether a block type is one of zero, DC, left, and top. If not, the inverse transform is performed and a residual video block is provided as residual information. When the block type is zero, inverse transform is bypassed. When the block type is DC, reduced complexity inverse transform of a DC coefficient is performing and a single residual coefficient is provided as residual information. When the block type is left, reduced complexity inverse transform of a left column of the input transform block is performed and a single column of residual coefficients is provided as residual information. When the block type is top, reduced complexity inverse transform of a top row is performed and a single row of residual coefficients is provided as residual information.05-19-2011
20150181211VIDEO INFORMATION PROCESSING SYSTEM WITH SELECTIVE CHROMA DEBLOCK FILTERING - A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder.06-25-2015

Patent applications by Zhongli He, Austin, TX US

Zhong Li He, Austin, TX US

Patent application numberDescriptionPublished
20120327303BACKLIT VIDEO DISPLAY WITH DYNAMIC LUMINANCE SCALING - A method of displaying an image defined by an input video signal on a backlit video device accommodates changes of luminance between successive frames of the input video signal. Changes of luminance distribution, which is a function of a distribution of pixel luminance values in the frames, between the successive frames are detected. Target adjustments to luminance of the backlight and to light transmission of the image panel for a current frame of the input video signal are defined to compensate luminance of the displayed image for the adjustment to luminance of the backlight. Actual adjustments to luminance of the backlight and to light transmission of the image panel for the current frame are functions of the target adjustments for the current frame and of the actual adjustments for a previous frame in proportions, which are a function of the changes detected of luminance distribution between successive frames.12-27-2012
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