| Patent application number | Description | Published |
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| 20110078521 | TRANSITION FAULT TESTING FOR A VON-VOLATILE MEMORY - A method is for testing a non-volatile memory. A base data pattern is defined for a first pageset of the non-volatile memory. The non-volatile memory has a plurality of pages which comprise words. The base pattern is arranged so that each bitpair of a plurality of bitpairs that includes one of a group consisting of even bitpairs and odd bitpairs formed from all of the words exhibits all possible bitpair transitions during sequential accesses of the pages of the plurality of pages. The base pattern is stored in the first pageset. The pages of the plurality of pages of the first pageset are accessed sequentially. | 03-31-2011 |
| 20120014179 | SOFT PROGRAM OF A NON-VOLATILE MEMORY BLOCK - A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition. | 01-19-2012 |
| 20120072794 | NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION - A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value. | 03-22-2012 |
| 20120113714 | METHOD FOR PROGRAMMING A MULTI-STATE NON-VOLATILE MEMORY (NVM) - A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage. | 05-10-2012 |
| 20120117307 | NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE - A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller. | 05-10-2012 |
| 20120131262 | Method and Apparatus for EEPROM Emulation for Preventing Data Loss in the Event of a Flash Block Failure - A defect resistant EEPROM emulator ( | 05-24-2012 |
| 20120201082 | ERASE RAMP PULSE WIDTH CONTROL FOR NON-VOLATILE MEMORY - A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block. | 08-09-2012 |
| 20120206973 | Digital Method to Obtain the I-V Curves of NVM Bitcells - A calibration table ( | 08-16-2012 |
| 20120327710 | ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY - A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A level of the voltage is compared to a reference. If the level of the voltage is below the reference, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells. | 12-27-2012 |
| 20120327720 | ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY USING VERIFY READ - A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A determination is made if the voltage insufficient for performing the write operation on the memory cells of the memory array. If a level of the voltage is insufficient, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells. The reduced number of memory cells is a first subset of the memory cells. | 12-27-2012 |
| 20130107621 | BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT | 05-02-2013 |
| 20130194874 | Dynamic Healing Of Non-Volatile Memory Cells - Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques. | 08-01-2013 |
| 20130238831 | METHOD FOR IMPLEMENTING SECURITY OF NON-VOLATILE MEMORY - An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship. | 09-12-2013 |
| 20130290797 | NON-VOLATILE MEMORY (NVM) RESET SEQUENCE WITH BUILT-IN READ CHECK - A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational. | 10-31-2013 |
| 20130290808 | ERASING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells. | 10-31-2013 |
| 20130308402 | TEST FLOW TO DETECT A LATENT LEAKY BIT OF A NON-VOLATILE MEMORY - A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level. | 11-21-2013 |
| 20130326285 | STRESS-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A NON-VOLATILE MEMORY ARRAY - A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level. | 12-05-2013 |
| 20140029351 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR PROGRAM/ERASE OPERATIONS TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations. | 01-30-2014 |
| 20140040687 | Non-Volatile Memory (NVM) with Imminent Error Prediction - A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated. | 02-06-2014 |
| 20140078829 | NON-VOLATILE MEMORY (NVM) WITH ADAPTIVE WRITE OPERATIONS - A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate. | 03-20-2014 |
| 20140098615 | LATENT SLOW BIT DETECTION FOR NON-VOLATILE MEMORY - In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold. | 04-10-2014 |
| 20140136928 | PROGRAMMING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells. | 05-15-2014 |
| 20140160869 | BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT - A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value. | 06-12-2014 |
| 20140204678 | DYNAMIC DETECTION METHOD FOR LATENT SLOW-TO-ERASE BIT FOR HIGH PERFORMANCE AND HIGH RELIABILITY FLASH MEMORY - A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM. | 07-24-2014 |
| 20140254285 | Temperature-Based Adaptive Erase or Program Parallelism - A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells. | 09-11-2014 |
| 20140269111 | NON-VOLATILE MEMORY (NVM) WITH BLOCK-SIZE-AWARE PROGRAM/ERASE - A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of the selected block; determining a set of program/erase voltages based on the array size and temperature from a temperature sensor; and programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block. | 09-18-2014 |
| 20150023106 | Adaptive Erase Recovery For Non-Volatile Memory (NVM) Systems - Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system. | 01-22-2015 |
| 20150049555 | Extended Protection For Embedded Erase Of Non-Volatile Memory Cells - Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (V | 02-19-2015 |
| 20150085593 | NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT - A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation. | 03-26-2015 |
| 20150117112 | ADAPTIVE ERASE METHODS FOR NON-VOLATILE MEMORY - A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks. | 04-30-2015 |
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| 20150034315 | VISCOSIFIED ACID FLUID AND METHOD FOR USE THEREOF - A method includes providing an oilfield treatment fluid including an aqueous HCl solution having greater than 15% HCl by weight, and a fixing agent (FA) in a molar ratio of FA:HCl of between 0.5 and 2.5 inclusive. The FA is urea and/or a urea derivative. The oilfield treatment fluid further includes a viscosifying agent that is not a plant-based polysaccharide gum. The method further includes providing the oilfield treatment fluid to a high pressure pump, and operating the high pressure pump to treat a formation fluidly coupled to a wellbore. | 02-05-2015 |
| 20150034318 | AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - A method of treating a formation includes preparing an aqueous solution having HCl in an amount between greater than 15% and 45.7% by weight, inclusive. The prepared aqueous solution includes a fixing agent (FA) present in a molar ratio of FA:HCl between 0.15 and 2.5 inclusive, where the FA is urea and/or a urea derivative, and further includes water present in an amount sufficient to dissolve the HCl and the FA. The aqueous solution includes substantially no polysaccharides. | 02-05-2015 |
| 20150037234 | AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - An aqueous solution includes HCl present in an amount exceeding 37% by weight. The solution further includes a fixing agent that is urea and/or a urea derivative. The fixing agent is present in the solution in a molar ratio of between 0.25 and 2.0 of fixing agent to HCl, inclusive. | 02-05-2015 |
| 20150114647 | AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Aqueous compositions contain hydrochloric acid at a concentration between 8 wt % and 28 wt % inclusive. The amino acid; hydrochloric acid mole ratio may be between 0.2 and 1.5. Sufficient water is present to dissolve the hydrochloric acid and the amino acid. Such compositions have utility as retarders for acid compositions employed in the stimulation of subterranean formations. Slowing the reaction between the acid and formation helps maximize formation permeability and productivity. | 04-30-2015 |
| 20150122485 | AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Oilfield treatment compositions contain water, hydrochloric acid at a concentration between 15 wt % and 45.7 wt % and a first and second fixing agent. The first fixing agent comprises urea, a urea derivative or both. The second fixing agent may be a mixture or amines and alcohols. These compositions provide corrosion inhibition when exposed to steel. The compositions may also contain an inhibitor aid. | 05-07-2015 |
| 20150122499 | AQUEOUS SOLUTION AND METHOD FOR USE THEREOF - Oilfield treatment compositions contain water, hydrochloric acid at a concentration between 15 wt % and 45.7 wt % and a first fixing agent. The first fixing agent comprises urea, a urea derivative or both. The molar ratio between the first fixing agent and water may be higher than or equal to 0.5, and urea is the dominant solvent species in the compositions. In these compositions the first fixing agent provides corrosion inhibition when exposed to steel. The compositions may also contain a second fixing agent and an inhibitor aid. | 05-07-2015 |
| 20150240147 | AQUEOUS SOLUTION AND METHODS FOR MANUFACTURE AND USE - Oilfield treatment compositions contain water, hydrochloric acid and urea. The urea and water may be present at a urea/water weight ratio between 0.8 and 12.0, and the hydrochloric acid and urea may be present at a urea/hydrochloric acid molar ratio between 0.1 and 0.5. The compositions are present as one liquid phase. The volumes of the compositions are substantially higher than those of the water volumes; consequently, the amount of water necessary to perform various well-service operations is lower. | 08-27-2015 |
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| 20150303932 | COMPARATOR TRACKING CONTROL SCHEME WITH DYNAMIC WINDOW LENGTH - A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on. | 10-22-2015 |
| 20150381130 | REDUCING AUDIO ARTIFACTS IN A SYSTEM FOR ENHANCING DYNAMIC RANGE OF AUDIO SIGNAL PATH - In accordance with embodiments of the present disclosure, an apparatus for providing an output signal to an audio transducer may include a control circuit. The control circuit may be configured to predict, based on a magnitude of a signal indicative of the output signal, an occurrence of an event for changing a selectable digital gain and a selectable analog gain and an audio signal path, and responsive to predicting the occurrence of the event, change, at an approximate time in which a zero crossing of the signal indicative of the output signal occurs, the selectable digital gain and the selectable analog gain. | 12-31-2015 |
| 20160072465 | SYSTEMS AND METHODS FOR GAIN CALIBRATION OF AN AUDIO SIGNAL PATH - A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error. | 03-10-2016 |
| 20160080862 | SYSTEMS AND METHODS FOR REDUCTION OF AUDIO ARTIFACTS IN AN AUDIO SYSTEM WITH DYNAMIC RANGE ENHANCEMENT - In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path. | 03-17-2016 |
| 20160080865 | SYSTEMS AND METHODS FOR REDUCTION OF AUDIO ARTIFACTS IN AN AUDIO SYSTEM WITH DYNAMIC RANGE ENHANCEMENT - In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path. | 03-17-2016 |
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| 20130002668 | SYSTEMS AND METHODS FOR DISPLAYING, VIEWING AND NAVIGATING THREE DIMENSIONAL REPRESENTATIONS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a three dimensional (3D) representation, where the multiple objects are visual representations of real objects, and display a subset of the objects and associated metadata in a shaped lens that is movable within the 3D representation in all three axes, where the subset of the objects displayed within the shaped lens are sized larger than the objects outside of the shaped lens. | 01-03-2013 |
| 20130002723 | SYSTEMS AND METHODS FOR DISPLAYING AND VIEWING DATA MODELS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a single pane, where the multiple objects are visual representations of real objects and the multiple objects are dynamically sized and spaced relative to one another to fit all of the objects in the single pane. The computer program product includes executable code that, when executed, causes the data processing apparatus to display a subset of the objects and associated metadata in an examination frame. The examination frame is sized to fit within the single pane, where the subset of the objects displayed within the examination frame are sized larger than the objects outside of the examination frame. | 01-03-2013 |
| 20130086507 | DISPLAY WINDOW WITH MULTI-LAYER, PARALLEL TAB DISPLAY - A layer manager provides at least two content layers within a user interface window of a software application. A tab manager provides at least two content tabs within at least one of the content layers. A transfer manager is configured to transfer at least one content tab between the at least two content layers. | 04-04-2013 |
| 20140111520 | USER-CENTRIC ANNOTATED LOCATION AWARE ASSET MAPPING - According to one general aspect, a method may include receiving a floor map indicating the structural layout of a predefined physical location. The method may also include receiving a point-of-interest (POI) data structure representing a POI and POI metadata associated with the POI. The method may include generating an annotated floor map, based upon the floor map and including a POI indicator, wherein the POI indicator is placed on the floor map at the location of an associated POI and indicates both the type of the associated POI and at least part of the status of the associated POI. The method may include displaying, via a display interface, at least a portion of the annotated floor map. | 04-24-2014 |
| 20140113559 | PROACTIVE ROLE AWARE ASSET MONITORING - According to one general aspect, a method may include establishing a short-range wireless communication between a user device and a point-of-interest (POI) device, wherein the POI device is associated with a POI data structure that represents a physical POI. The method may include receiving a request to perform a POI action in regards to the physical POI. The method may include causing the POI action to be performed. | 04-24-2014 |
| 20140114931 | MANAGEMENT OF ANNOTATED LOCATION AWARE ASSETS - According to one general aspect, a method may include storing, in a memory device, a plurality of floor maps, each floor map indicating the structural layout of a respective predefined physical location. The method may include storing, in a memory device, a plurality of point-of-interest (POI) data structures. Each POI data structure may include a physical location of an associated POI. The method may include receiving a floor map request from a client computing device, wherein the floor map request includes a requested location. The method may include based upon the location included by the floor map request, selecting a selected floor map and a selected subset of the plurality of POI data structures. The method may include transmitting, to the client computing device, a response to the floor map request based upon the selected floor map and the selected POI data structures. | 04-24-2014 |
| 20140365121 | USER-CENTRIC ANNOTATED LOCATION AWARE ASSET MAPPING - According to one general aspect, a method may include receiving a floor map indicating a structural layout of a physical location, receiving a point-of-interest (POI) data structure representing a POI and POI metadata associated with the POI, POI data structure including a location of an associated POI that is associated with the POI, and the POI metadata including a POI type indicating a type of the associated POI, and a POI status indicating the status of the associated POI, annotating the floor map by overlaying on the selected floor map an indicator for each selected POI data structure such that the indicator is placed on the floor map at a location representing the physical location of the respective associated POI and indicates the type of the associated POI and the status of the associated POI, displaying a portion of the annotated floor map, and initiating a POI action. | 12-11-2014 |
| 20140365489 | MANAGEMENT OF ANNOTATED LOCATION AWARE ASSETS - A method may include storing a plurality of floor maps, each floor map indicating a structural layout of a respective physical location, storing a plurality of point-of-interest (POI) data structures, each POI data structure including a physical location of an associated POI that is associated with the respective POI data structure, receiving a floor map request, the floor map request including a requested location, based upon the location included by the floor map request, selecting a floor map and a subset of the plurality of POI data structures, for each of the subset of the plurality of POI data structures, receiving metadata from the associated POI, the metadata indicating a status of the associated POI, and transmitting, to the client computing device and in response to the floor map request, the selected floor map and the selected POI data structures. | 12-11-2014 |
| 20150161806 | SYSTEMS AND METHODS FOR DISPLAYING AND VIEWING DATA MODELS - A computer program product is tangibly embodied on a computer-readable medium and includes executable code that, when executed, is configured to cause a data processing apparatus to display multiple objects in a single pane, where the multiple objects are visual representations of real objects and the multiple objects are dynamically sized and spaced relative to one another to fit all of the objects in the single pane. The computer program product includes executable code that, when executed, causes the data processing apparatus to display a subset of the objects and associated metadata in an examination frame. The examination frame is sized to fit within the single pane, where the subset of the objects displayed within the examination frame are sized larger than the objects outside of the examination frame. | 06-11-2015 |
| 20160078012 | SYSTEMS AND METHODS FOR FORMLESS INFORMATION TECHNOLOGY AND SOCIAL SUPPORT MECHANICS - A system includes a user interface having a text input box configured to receive input from a user, the input including text and/or an action indicator, and a response area for displaying results and/or action selection buttons in response to the input from the text input box. The system includes an application engine that receives the input from the text input box as a user types each character into the text input box, performs a search and present results to the search in the response area, in response to receiving additional text input from the text input box, performs the search and presents updated results to the search in the response area, and in response to receiving text and an action indicator from the text input box, causes an action corresponding to the action indicator to be performed and causes a change to the user interface corresponding to the action. | 03-17-2016 |
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| 20100327765 | LOW ENERGY TRANSFER MODE FOR AUXILIARY POWER SUPPLY OPERATION IN A CASCADED SWITCHING POWER CONVERTER - A cascaded power converter having an auxiliary power supply operated from the second switching power stage provides efficient operation by activating the auxiliary power supply early in the startup process. A low energy transfer operating mode is initiated in the second switching power stage to charge the auxiliary power supply output without generating significant disruption at the load. After the first switching power stage is started and the intermediate node voltage has increased to a level sufficient to operate the second switching power stage, the final switching power stage enters a normal operating mode. The low energy transfer operating mode has a substantially reduced switching rate and pulse width from that of the normal operating mode. | 12-30-2010 |
| 20120153858 | Switching Parameter Based Discontinuous Mode-Critical Conduction Mode Transition - An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage. | 06-21-2012 |
| 20120306406 | CONTROL DATA DETERMINATION FROM PRIMARY-SIDE SENSING OF A SECONDARY-SIDE VOLTAGE IN A SWITCHING POWER CONVERTER - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the controller determines the one or more switching power converter control parameters using a resonant period factor from a reflected secondary-side voltage and an occurrence of an approximate zero voltage crossing of the secondary-side voltage during a resonant period of the secondary-side voltage. In at least one embodiment, the switching power converter control parameters include (i) an estimated time of a minimum value of the secondary-side voltage during the resonant period and (ii) an estimated time at which a current in the secondary-side of the transformer decayed to approximately zero. | 12-06-2012 |
| 20120306407 | Primary-Side Control Of A Switching Power Converter With Feed Forward Delay Compensation - An electronic system includes controller to control a switching power converter to provide power to a load. To control the amount of power provided to the load, in at least one embodiment, the controller senses a current value representing a current in the switching power converter and detects when the current value reaches a target peak value. However, due to delays in the controller and/or the switching power converter, the detected target peak value will not be the actual current peak value generated by the switching power converter. In at least one embodiment, the controller adjusts the detected target peak value with a post-detection delay compensation factor to generate a delay compensated current value that more accurately represents an actual peak current value associated with the current in the switching power converter. | 12-06-2012 |
| 20130002163 | Input Voltage Sensing For A Switching Power Converter And A Triac-Based Dimmer - An electronic lighting system and method described herein control energy provided to an electronic lighting device, such as one or more light-emitting diodes (LEDs) and/or compact fluorescent lamps (CELs), of the electronic lighting system. A triac-based dimmer phase cuts a line voltage provided to the electronic lighting system. A controller of the electronic lighting system utilizes a probing system to overcome idiosyncrasies of the triac-based dimmer to allow the controller to probe and sense the line voltage. To reduce energy consumption, rather than probing each cycle of the output voltage of the triac-based dimmer, the controller periodically or intermittently probes the output voltage of the triac-based dimmer. | 01-03-2013 |
| 20130154495 | Adaptive Current Control Timing and Responsive Current Control for Interfacing with a Dimmer - In at least one embodiment, an electronic system adapts current control timing for half line cycle of a phase-cut input voltage and responsively controls a dimmer current in a power converter system. The adaptive current control time and responsive current control provides, for example, interfacing with a dimmer. The electronic system and method include a dimmer, a switching power converter, and a controller to control the switching power converter and controls a dimmer current. In at least one embodiment, the controller determines a predicted time period from a zero crossing until a leading edge of a phase-cut input voltage and then responsively controls the dimmer current to, for example, reduce current and voltage perturbations (referred to as “ringing”), improve efficiency, and reduce an average amount of power handled by various circuit components. | 06-20-2013 |
| 20130154496 | MULTI-MODE FLYBACK CONTROL FOR A SWITCHING POWER CONVERTER - In at least one embodiment, an electronic system and method includes a controller to control a switching power converter in at least two different modes of operation depending on whether the controller detects a dimmer or not and/or whether a load requests more power than either of the two operational modes can provide. In at least one embodiment, the controller detects whether a dimmer is phase cutting an input voltage to a switching power converter. The controller operates the switching power converter in a first mode if the dimmer is detected, and the controller operates the switching power converter in a second mode if the dimmer is not detected. The controller also transitions between operating the switching power converter in the first mode and the second mode if a status of detection of the dimmer changes. | 06-20-2013 |
| 20140028095 | ACCELERATION OF OUTPUT ENERGY PROVISION FOR A LOAD DURING START-UP OF A SWITCHING POWER CONVERTER - An electronic system and method include a controller to operate in a start-up mode to accelerate driving a load to an operating voltage and then operates in a post-start-up mode. A start-up condition occurs when the controller detects that a load voltage is below a predetermined voltage threshold level. The predetermined voltage threshold level is set so that the controller will boost the voltage to an operating value of a load voltage at a faster rate than during normal, steady-state operation. The controller causes a switching power converter to provide charge to the load at a rate in accordance with a start-up mode until reaching an energy-indicating threshold. When the energy-indicating threshold has been reached, the controller causes the switching power converter to (i) decrease the amount of charge provided to the load relative to the charge provided during the start-up mode and (ii) operate in a distinct post-start-up-mode. | 01-30-2014 |
| 20140028213 | ACTIVE THERMAL PROTECTION FOR SWITCHES - A system and method include a controller that reduces power dissipated by a switch, such as a source-controlled field effect transistor, when an estimated amount of power dissipated by the switch exceeds a predetermined threshold. Reducing the power dissipated by the switch prevents damage to the switch due to overheating. The controller determines the estimated amount of power dissipated by the switch using actual drain-to-source current and drain voltage data. In at least one embodiment, the controller includes a fail-safe, estimated power dissipation determination path that activates when the drain voltage data fails a reliability test. Additionally, in at least one embodiment, the controller includes a model of thermal characteristics of the switch. In at least one embodiment, the controller utilizes real-time estimated power dissipation by the switch and the model to determine when the estimated power dissipated by the switch exceeds a power dissipation protection threshold. | 01-30-2014 |
| 20140252981 | Utilizing Secondary-Side Conduction Time Parameters of a Switching Power Converter to Provide Energy to a Load - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the switching power converter utilizes a transformer to transfer energy from a primary-side of the transformer to a secondary-side of the transformer. In at least one embodiment, the switching power converter control parameters includes a secondary-side conduction time delay that represents a time delay between when the primary-side ceases conducting a primary-side current and the secondary-side begins to conduct a secondary-side current. In at least one embodiment, determining and accounting for this secondary-side conduction time delay increases the prediction accuracy of the secondary-side current value and accurate delivery of energy to a load when the controller does not directly sense the secondary-side current provided to the load. | 09-11-2014 |
| 20140252990 | Quantization Error Reduction in Constant Output Current Control Drivers - An electronic system and method includes a controller to control a switching power converter in at least two different modes of operation, a normal mode and an error reduction mode. The controller controls an amount of charge pushed (i.e. delivered) by the switching power converter to a load to reduce a charge quantization error. The charge quantization error represents an amount of charge pushed to the load beyond a target charge amount. The controller determines an amount of charge to be pushed to the toad. Based on the amount of charge to be pushed to the load, the controller generates a current control signal that controls a current control switch in the switching power converter. Determination of the control signal depends on whether the controller is operating in normal mode or error reduction mode. The controller attempts to reduce the charge quantization error to avoid power fluctuations. | 09-11-2014 |
| 20150340955 | Switching Parameter Based Discontinuous Mode-Critical Conduction Mode Transition - An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage. | 11-26-2015 |
| 20150340956 | Utilizing Secondary-Side Conduction Time Parameters of a Switching Power Converter to Provide Energy to a Load - A power distribution system includes controller of a switching power converter to control the switching power converter and determine one or more switching power converter control parameters. In at least one embodiment, the switching power converter utilizes a transformer to transfer energy from a primary-side of the transformer to a secondary-side of the transformer. In at least one embodiment, the switching power converter control parameters includes a secondary-side conduction time delay that represents a time delay between when the primary-side ceases conducting a primary-side current and the secondary-side begins to conduct a secondary-side current. In at least one embodiment, determining and accounting for this secondary-side conduction time delay increases the prediction accuracy of the secondary-side current value and accurate delivery of energy to a load when the controller does not directly sense the secondary-side current provided to the load. | 11-26-2015 |
| 20150351178 | Adaptive Current Control Timing and Responsive Current Control for Interfacing with a Dimmer - In at least one embodiment, an electronic system adapts current control timing for half line cycle of a phase-cut input voltage and responsively controls a dimmer current in a power converter system. The adaptive current control time and responsive current control provides, for example, interfacing with a dimmer. The electronic system and method include a dimmer, a switching power converter, and a controller to control the switching power converter and controls a dimmer current. In at least one embodiment, the controller determines a predicted time period from a zero crossing until a leading edge of a phase-cut input voltage and then responsively controls the dimmer current to, for example, reduce current and voltage perturbations (referred to as “ringing”), improve efficiency, and reduce an average amount of power handled by various circuit components. | 12-03-2015 |
| Patent application number | Description | Published |
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| 20080240252 | SIMPLIFIED DEBLOCK FILTERING FOR REDUCED MEMORY ACCESS AND COMPUTATIONAL COMPLEXITY - A method of simplifying deblock filtering of video blocks of an enhanced layer of scalable video information is disclosed which includes selecting an adjacent pair of video blocks, determining whether boundary strength of the video blocks is a first value, evaluating first conditions using component values of a first component line if the boundary strength is not the first value, and bypassing deblock filtering between the video blocks if the boundary strength is the first value or if any of the first conditions is false. The method may include bypassing evaluating conditions and deblock filtering associated with the maximum boundary strength. The method may include bypassing evaluating second conditions and bypassing corresponding deblock filtering if the intermediate edge is a horizontal edge. The method may include bypassing less efficient memory reads associated with component values used for evaluating the second conditions. | 10-02-2008 |
| 20090060035 | TEMPORAL SCALABILITY FOR LOW DELAY SCALABLE VIDEO CODING - A method of processing video information which includes receiving encoded video information including an encoded base layer frame and encoded enhanced layer frames for providing temporal scalability, decoding the encoded video information in display order, and using a decoded first enhanced layer frame as a reference frame for decoding a second enhanced layer frame for forward prediction. Processing the video information in display order and using a decoded enhanced layer frame as a reference frame for processing another enhanced layer frame for forward prediction reduces coding latency for achieving temporal scalability for low delay scalable video coding. The coding memory space may also be reduced as compared to bidirectional prediction coding since the number of reference frames used for coding may be reduced. | 03-05-2009 |
| 20100260269 | VIDEO DECODING WITH ERROR DETECTION AND CONCEALMENT - A system and method of decoding input video information is disclosed which includes performing error detection for each video block of a frame, determining whether a scene change occurs for the frame, and when an error is detected in a video block, performing spatial concealment by concealing error of the erroneous video block using neighboring video information within the frame when the erroneous video block is intraframe encoded or when a scene change is detected for the frame, or performing temporal concealment by replacing the erroneous video block with a reference video block from a reference frame when the erroneous video block is interframe encoded and when a scene change is not detected for the frame. The method may further include detecting false frames based on comparing current and new frame number and picture order count values of a new slice. | 10-14-2010 |
| 20110032430 | DYNAMIC COMPENSATION OF DISPLAY BACKLIGHT BY ADAPTIVELY ADJUSTING A SCALING FACTOR BASED ON MOTION - A video adjustment system for processing video information is disclosed which includes a motion analyzer and an adjustment module. The motion analyzer determines a motion level metric of the video information based on at least one motion parameter. The adjustment adjusts an initial dynamic light scaling factor to provide an adjusted dynamic light scaling factor based on the motion level. The dynamic light scaling factor may be used for luminance compensation and backlight display scaling. The motion level may be based on any type of motion information, such as motion vector information or information indicating a scene change. A distortion module may perform a distortion evaluation of the video information for calculating the initial scaling factor. Alternatively, the distortion module may include a memory which stores predetermined scaling factors based on statistical distortion level characterization. | 02-10-2011 |
| 20110116539 | METHOD AND APPARATUS FOR VIDEO DECODING WITH REDUCED COMPLEXITY INVERSE TRANSFORM - A method of reducing processing of fast inverse transform of an input transform block by a video decoder includes determining whether a block type is one of zero, DC, left, and top. If not, the inverse transform is performed and a residual video block is provided as residual information. When the block type is zero, inverse transform is bypassed. When the block type is DC, reduced complexity inverse transform of a DC coefficient is performing and a single residual coefficient is provided as residual information. When the block type is left, reduced complexity inverse transform of a left column of the input transform block is performed and a single column of residual coefficients is provided as residual information. When the block type is top, reduced complexity inverse transform of a top row is performed and a single row of residual coefficients is provided as residual information. | 05-19-2011 |
| 20150181211 | VIDEO INFORMATION PROCESSING SYSTEM WITH SELECTIVE CHROMA DEBLOCK FILTERING - A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder. | 06-25-2015 |
